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Video Scaler v4.0 User Guide
UG805 March 1, 2011
Appendix C:
System Level Design
Scaler WRITE-port
•
For the port that feeds from the video scaler out to the memory,
ensure that there is a
FIFO of a size equal to or greater than the maximum line length anticipated to be
output by the scaler
. Ideally, set this to the
next power of 2 above the maximum
output line length.
For this example, the max line length is 1280, so the FIFO has been
set to 2048 pixels.
•
For systems like the VFBC, which have a FIXED threshold for the ALMOST
full/empty flags, set this value to the maximum output line-length. This ensures that
the
wd_almost_full
flag will not be driven low until
there is sufficient space in
the FIFO for an entire line of video data.
Cropping from Memory
Controlling the VDMA dynamically (e.g., from MicroBlaze or other processor) allows you
to request any rectangle from any where in the image in memory, and change the position
and dimensions of this rectangle on a frame-by frame basis. One complication of doing this
with the VFBC is that the FIFO almost full/empty thresholds are FIXED at compile-time.
According to the guidelines above, it is necessary to set the thresholds to the maximum line
length. Yet, when cropping from memory, you will be requesting a rectangle of a smaller
width than the maximum line length. Consequently, the final lines may not be read from
memory correctly,
resulting in some distortion at the bottom of the image.
To work around this issue, it is necessary, and safe, to
request more lines than you want to
scale.
This keeps the FIFO topped up with data. This can be achieved by setting the
VDMA
Read Vsize
register (address offset 0x28)
to a number greater than you want. See the
VDMA Data Sheet
for more information. The scaler register settings should
not
be set
differently to your desired values.
OSD Configuration
The OSD is configured for two layers. The first layer is video data read from VDMA2. The
second layer is text overlay.
EDK MHS File Text
The following is an example EDK MHS file insert for the system described.
Note:
This is NOT a complete design, but provides some idea as to the construction of a video
scaler system in EDK.
BEGIN vdma
PARAMETER INSTANCE = vdma_0
PARAMETER HW_VER = 1.01.a
PARAMETER C_MPMC_BASEADDR = 0x10000000
PARAMETER C_MPMC_HIGHADDR = 0x1fffffff
PARAMETER C_GEN_RESET = 1
PARAMETER C_DATA_WIDTH = 16
PARAMETER C_NUM_FSTORES = 5
PARAMETER C_CROP_ENABLE = 1
PARAMETER C_DMA_TYPE = 2
PARAMETER C_BASEADDR = 0xcb480000
PARAMETER C_HIGHADDR = 0xcb48ffff
BUS_INTERFACE SPLB = mb_plb
BUS_INTERFACE XIL_VFBC = vdma_0_XIL_VFBC
BUS_INTERFACE XIL_WD_VDMA = tpg_0_XIL_VDMA_TPG_OUT
PORT IP2INTC_Irpt = vdma_0_IP2INTC_Irpt
Содержание LogiCORE IP
Страница 1: ...LogiCORE IP Video Scaler v4 0 User Guide UG805 March 1 2011...
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Страница 14: ...14 www xilinx com Video Scaler v4 0 User Guide UG805 March 1 2011 Preface About This Guide...
Страница 18: ...18 www xilinx com Video Scaler v4 0 User Guide UG805 March 1 2011 Chapter 1 Introduction...
Страница 20: ...20 www xilinx com Video Scaler v4 0 User Guide UG805 March 1 2011 Chapter 2 Overview...
Страница 70: ...70 www xilinx com Video Scaler v4 0 User Guide UG805 March 1 2011 Chapter 9 Performance...
Страница 74: ...74 www xilinx com Video Scaler v4 0 User Guide UG805 March 1 2011 Appendix A Use Cases...
Страница 92: ...92 www xilinx com Video Scaler v4 0 User Guide UG805 March 1 2011 Appendix B Programmer Guide...
