Xilinx LogiCORE IP, Руководство пользователя

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Video Scaler v4.0 User Guide www.xilinx.com 83
UG805 March 1, 2011
Register Definitions
Table B-20: Coefficient Phase and Tap Read Address Register
0x0048 coef_mem_rd_addr R/W
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1 0
Reserved Phase Reserved Tap
Name Bits Description
Coeff Readback
Phase
13:8
Coefficient phase to be read from the scaler
Coeff Readback Bank 3:0 Coefficient tap to be read from scaler
Table B-21: Coefficient Memory Readback Output Register
0x004c coef_mem_rd_addr R
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1 0
Reserved Coeff Readback Output
Name Bits Description
Coeff Readback
Output
15:0
Coefficient readout from the scaler
Table B-22: Version Register
0x00F0 Version R
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9 8 7 6 5 4 3 2 1 0
HW Version
Name Bits Description
HW Version 31:0 Hard-coded hardware version register
Table B-23: Software Reset Register
0x0100 Software_Reset W
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Reserved d
Name Bits Description
Soft_Reset_Value 31:0
Soft Reset to reset the registers and IP core, data Value
provided by the EDK create peripheral utility