Vmetro VBAT-PB, Руководство пользователя

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3 Functional description
Sampling methods
The principal task of the VBT-325 is sampling the bus activity. While timing
(asynchronous) sampling is straight forward in the sense that samples are taken
at fixed time intervals,
state (synchronous) sampling depends heavily on the
bus protocol.
In order to fully interpret what is seen in the trace display when state sampling
is used, it may be necessary to understand how the analyzer samples the bus.
Thus, a detailed explanation of the employed state sampling methods is given
below.
VMEbus state sampling
To properly capture all information of the transactions on a VMEbus backplane
during state analysis, the VMEbus sampling logic latches bus signals both at the
completion of a bus arbitration and at each data phase. This is for normal
cycles, Read-Modify-Write cycles and Block cycles, which include SSBLT
cycles.
Bus Request latching
Normally, the active bus request signal (BRx*) on the VME backplane goes
away immediately after the corresponding bus grant (BGx)* is taken low, too
early for being sampled together with address, data etc. on the falling edge of
DTACK* or BERR (described below). To ensure capture of the active bus
request(s) even during state sampling, the pending BRx* may be latched
internally until DTACK* goes low.
(This feature can be turned off by the command 'Edit/Sampling
m o d e / O p t i o n s / S t a t e S a m p l i n g o p t i o n s ' . )
Bus Grant latching - BgL
A VME system arbiter completes an arbitration by issuing one of four Bus
Grants (BG3-0*), and when this is received by a bus master with pending bus
request, it asserts BBSY*. This causes the Bus Grant to go away immediately,
so in order to keep track on which bus level the following transactions belong
to it is necessary to store the actual bus grant at falling edge of BBSY*. The
VBT-325 stores information about the active bus grant as an internal two-bit
value called
Bus Level, (or "Bus Grant Level"), shown as BgL in the trace. In
addition there is an extra bit that is set if the VBT-325 sees BBSY* being
asserted without any valid Bus Grant, a situation that will occur if the VBT-325
is located to the right of the granted bus master in the card crate. (Refer to
daisy-chain considerations in the Installation chapter). Information about the
actual bus level is presented in the trace as a number from 0 to 3, or as a '-'
signifying "No bus grant detected".
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