5.9.2.4 Phase offset and execution of OB 33 and OB 34
The CPU offers additional cyclic interrupts, which interrupt the cyclic
processing in certain distances. Point of start of the time interval is
the change of operating mode from STOP to RUN. To avoid that the
cyclic interrupts of different cyclic interrupt OBs receive a start
request at the same time and so a time out may occur, there is the
possibility to set a phase offset respectively a time of execution.
n
The
phase offset
(0 ... 60000ms) serves for distribution processing
times for cyclic interrupts across the cycle. Default: 0
n
The time intervals, in which the cyclic interrupt OB should be pro-
cessed may be entered with
execution
(1 ... 60000ms). Default:
OB 33: 500ms, OB 34: 200ms
5.9.2.5 Priority of OB 28, OB 29, OB 33 and OB 34
The priority fixes the order of interrupts of the corresponding interrupt
OB. Here the following priorities are supported: 0 (Interrupt-OB is
deactivated), 2, 3, 4, 9, 12, 16, 17, 24. Default: 24
5.10 Project transfer
There are the following possibilities for project transfer into the CPU:
n
Transfer via MPI/PROFIBUS
n
Transfer via Ethernet
n
Transfer via MMC
5.10.1
Transfer via MPI/PROFIBUS
For transfer via MPI/PROFIBUS there is the following interface:
n
X2: MPI interface
n
X3: PROFIBUS interface
The structure of a MPI net is electrically identical with the structure of
a PROFIBUS net. This means the same rules are valid and you use
the same components for the build-up. The single participants are
connected with each other via bus interface plugs and PROFIBUS
cables. Please consider with the CPU 315-2AG13 that the total exten-
sion of the MPI net does not exceed 50m. Per default the MPI net
runs with 187.5kbaud. VIPA CPUs are delivered with MPI address 2.
The MPI programming cables are available at VIPA in different var-
iants. The cables provide a RS232 res. USB plug for the PC and a
bus enabled RS485 plug for the CPU. Due to the RS485 connection
you may plug the MPI programming cables directly to an already
plugged plug on the RS485 jack. Every bus participant identifies itself
at the bus with an unique address, in the course of the address 0 is
reserved for programming devices.
Overview
General
Net structure
MPI programming cable
VIPA System 300S CPU
Deployment CPU 315-2AG13
Project transfer > Transfer via MPI/PROFIBUS
HB140 | CPU | 315-2AG13 | GB | Rev. 14-40
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