Viewmax VM032, Руководство по эксплуатации

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Page 52
DRAM CAS# Latency
When the
Configuration DRAM Timing by SPD
sets to [Disabled], the field is adjustable. This controls the
CAS latency, which determines the timing delay (in clock cycles) before SDRAM starts a read command
after receiving it.
DRAM RAS# to CAS# Delay
When the
Configuration DRAM Timing by SPD
sets to [Disabled], the field is adjustable. When DRAM is
refreshed, both rows and columns are addressed separately. This setup item allows you to determine the
timing of the transition from RAS (row address strobe) to CAS (column address strobe). The smaller the
clock cycles, the faster the DRAM performance.
DRAM RAS# Precharge
When the
Configuration DRAM Timing by SPD
sets to [Disabled], this field is adjustable. This field is
adjustable. This setting controls the number of cycles for Row Address Strobe (RAS) to be allowed for
precharge. If insufficient time is allowed for the RAS to accumulate its charge before DRAM refresh, refresh
may be incomplete and DRAM may fail to retain data. This item applies only when synchronous DRAM is
installed in the system.
DRAM RAS# Activate to Precharge
When the
Configuration DRAM Timing by SPD
sets to [Disabled], this field is adjustable. This field is
adjustable. This setting controls the number of cycles for Row Address Strobe (RAS) to be allowed for
precharge. If insufficient time is allowed for the RAS to accumulate its charge before DRAM refresh, refresh
may be incomplete and DRAM may fail to retain data. This item applies only when synchronous DRAM is
installed in the system.
DRAM TRFC
When the
Configuration DRAM Timing by SPD
sets to [Disabled], the field is adjustable. This setting
determines the time RFC takes to read from and write to a memory cell.
DRAM TWR
When the
Configuration DRAM Timing by SPD
sets to [Disabled], the field is adjustable. Minimum time
interval between end of write data burst and the start of a precharge command. Allows sense amplifiers to
restore data to cells.
DRAM TWTR
When the
Configuration DRAM Timing by SPD
sets to [Disabled], the field is adjustable. Minimum time
interval between end of write data burst and the start of a column-read command. It allows I/O gating to
overdrive sense amplifiers before read command starts.
DRAM TRRD
When the
Configuration DRAM Timing by SPD
sets to [Disabled], the field is adjustable. Specifies the
active-to-active delay of different banks. Time interval between a read and a precharge command.
DRAM TRTP
When the
Configuration DRAM Timing by SPD
sets to [Disabled], the field is adjustable. Time interval
between a read and a precharge command.
FSB/Memory Ratio
This item will allow you to adjust the FSB/Ratio of memory.
Adjusted DDR Memory Frequency
It shows the adjusted DDR memory frequency. Read-only.
Auto Disable DIMM/PCI Frequency
When set to [Enabled], the system will remove (turn off) clocks from empty DIMM and PCI slots to minimize the
electromagnetic interference (EMI).
Memory Voltage (V)
This item will allow you to adjust the Memory voltage.