VIA Technologies SOM-9X35, Руководство по конструкции

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Carrier Board Design Guide for SOM-9X35 Module
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List of Figures
Figure 01: Schematic conventions ......................................................................................................................... 3
Figure 02: Microstrip PCB stack-up example ......................................................................................................... 4
Figure 03: Stripline PCB stack-up example ............................................................................................................ 4
Figure 04: 6-Layer PCB board stack-up detail ........................................................................................................ 5
Figure 05: Point-to-point and multi-drop examples ............................................................................................. 6
Figure 06: Daisy-chain example ............................................................................................................................. 6
Figure 07: Alternate multi-drop example .............................................................................................................. 6
Figure 08: Single-ended trace width and spacing example ................................................................................... 7
Figure 09: Differential trace width and spacing example ...................................................................................... 7
Figure 10: Suggested clock trace spacing .............................................................................................................. 8
Figure 11: Clock trace layout in relation to the ground plane ............................................................................... 8
Figure 12: Series termination for multiple clock loads .......................................................................................... 8
Figure 13: Use 135° bends instead of 90° .............................................................................................................. 9
Figure 14: Suggested minimum distance and segment length at bends ............................................................... 9
Figure 15: Try to increase spacing between traces whenever it is possible .......................................................... 9
Figure 16: Avoid stub traces by daisy chain routing ............................................................................................ 10
Figure 17: Remove ground plane under large pads ............................................................................................. 10
Figure 18: Do not put any components or vias between differential pairs ......................................................... 11
Figure 19: Place vias symmetrical ........................................................................................................................ 11
Figure 20: Route pairs on the same layer, place same amount of vias ................................................................ 11
Figure 21: Route pairs on the same layer, place same amount of vias ................................................................ 12
Figure 22: Add length correction to the mismatching point ................................................................................ 12
Figure 23: Place length compensation close to a bend ....................................................................................... 12
Figure 24: Length differences need to be compensated in each segment .......................................................... 13
Figure 25: Pairs within same Interface should be routed preferable on same layer ........................................... 13
Figure 26: Preferred symmetrical breakout ......................................................................................................... 13
Figure 27: Preferred breakout of differential pairs .............................................................................................. 14
Figure 28: SOM-9X35 module placement example on the carrier board ............................................................ 15
Figure 29: Dimensions of the SOM-9X35 module ............................................................................................... 16
Figure 30: Dimensions of the reference carrier board ........................................................................................ 16
Figure 31: Dimensions of the M.2 slot (top view) ............................................................................................... 17
Figure 32: Dimensions of the M.2 slot (side view) .............................................................................................. 17
Figure 33: M.2 slot placement ............................................................................................................................. 18
Figure 34: M.2 slot reference circuitry (part 1) ................................................................................................... 28
Figure 35: M.2 slot reference circuitry (part 2) ................................................................................................... 29
Figure 36: M.2 slot reference circuitry (part 3) ................................................................................................... 29
Figure 37: HDMI routing topology ....................................................................................................................... 30
Figure 38: HDMI differential trace width and spacing example .......................................................................... 31
Figure 39: HDMI single-ended trace width and spacing example ....................................................................... 31
Figure 40: HDMI reference circuitry (Part 1) ....................................................................................................... 32
Figure 41: HDMI reference circuitry (Part 2) ....................................................................................................... 33
Figure 42: HDMI reference circuitry (Part 3) ....................................................................................................... 33
Figure 43: MIPI DSI routing topology .................................................................................................................. 34
Figure 44: MIPI DSI differential trace width and spacing example ...................................................................... 35
Figure 45: MIPI DSI reference circuitry ................................................................................................................ 36
Figure 46: LCD backlight & bias voltage reference circuitry ................................................................................ 37
Figure 47: LVDS routing topology ........................................................................................................................ 38
Figure 48: LVDS differential trace width and spacing example ............................................................................ 38
Figure 49: LVDS reference circuitry ...................................................................................................................... 40
Figure 50: MIPI CSI routing topology ................................................................................................................... 42
Figure 51: MIPI CSI differential trace width and spacing example ...................................................................... 42
Figure 52: Camera main clock oscillator reference circuitry ................................................................................ 45
Figure 53: Camera I2C Bus level shift reference circuitry .................................................................................... 46
Figure 54: Camera control pin level shift reference circuitry ............................................................................... 46
Figure 55: Camera power control reference circuitry .......................................................................................... 47
Figure 56: MIPI 4-lane camera reference circuitry (Part 1) .................................................................................. 47