Carrier Board Design Guide for SOM-9X35 Module
8
2.2.3
General Clock Routing Considerations
The clock routing guidelines are listed below:
• The recommended clock trace width is 5mil.
• The minimum space between one clock trace and adjacent clock traces is 20mil. The minimum space
from one segment of a clock trace to other segments of the same clock trace is at least two times of
the clock width. That is, more space is needed from one clock trace to others or its own trace to avoid
signal coupling (see Figure 10).
• The clock traces should be parallel to their reference ground planes. That is, a clock trace should be right
beneath or on top of its reference ground plane (see Figure 11).
• The series terminations (damping resistors) are needed for all clock signals (typically 0Ω to 47Ω). When
two loads are driven by one clock signal, the series termination layout is shown in Figure 12. When
multiple loads (more than two) are applied, a clock buffer solution is preferred.
• Isolating clock synthesizer power and ground planes through ferrite beads or narrow channels (typically
20mil to 50mil wide) is preferred.
• No clock traces on the internal layer if a 6-layer board is used.
Figure 10: Suggested clock trace spacing
Figure 11: Clock trace layout in relation to the ground plane
Figure 12: Series termination for multiple clock loads