Carrier Board Design Guide for SOM-9X35 Module
53
S
W
S
SDC Signal
Single-ended
Reference Plane
Sig
Figure 64: SDC single-ended trace width and spacing example
Metrics
Information/Design Guidance
General Information
Data rate
208MHz
Impedance
Single-end
Main route
50Ω ± 5%
Connector
50Ω ± 20%
Length match (including
SOM-9X35)
Between clock and data
<27mil
Maximum trace length
6000 mil
Spacing
Spacing to all other signals
2 x line width
Spacing data lane-to-lane
2 x line width
Table 30: SDC layout guidelines
The carrier board SDC trace length and mismatch calculations should take into account consider the SDIO bus
from the SOM-9X35 module.
Net Name
Trace
Length
(mil)
Length
Spec (mil)
Length
Mismatch
(mil)
Length
Mismatch
Spec (mil)
Total
Delay
(Trace +
Via) (ps)
Delay
Mismatch
(ps)
Delay
Mismatch
Spec (ps)
Notes
MSDC1_CLK
2418.60
6000
404.16
MSDC1_CMD 2363.90
-54.70
67.50
404.38
0.22
10
Refer to
MSDC1_
CLK
MSDC1_DAT0 2393.46
-25.14
404.08
-0.08
10
MSDC1_DAT1 2393.93
-24.67
404.28
0.12
10
MSDC1_DAT2 2366.33
-52.28
404.06
-0.10
10
MSDC1_DAT3 2367.25
-51.35
404.36
0.20
10
Table 31:
SOM-9X35 SDC trace & via delay
