Technical description
3 Supporting functions
3.10 System clock and
synchronization
VM259.EN007
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***) Set the DI delay to its minimum and the polarity such that the leading
edge is the synchronizing edge.
Synchronisation with DI
Clock can be synchronized by reading minute pulses from
digital inputs, virtual inputs or virtual outputs. Sync source is
selected with SyncDI setting. When rising edge is detected from
the selected input, system clock is adjusted to the nearest
minute. Length of digital input pulse should be at least 50 ms.
Delay of the selected digital input should be set to zero.
Synchronisation correction
If the sync source has a known offset delay, it can be
compensated with SyOS setting. This is useful for
compensating hardware delays or transfer delays of
communication protocols. A positive value will compensate a
lagging external sync and communication delays. A negative
value will compensate any leading offset of the external synch
source.
Sync source
When the device receives new sync message, the sync source
display is updated. If no new sync messages are received within
next 1.5 minutes, the device will change to internal sync mode.
Deviation
The time deviation means how much system clock time differs
from sync source time. Time deviation is calculated after
receiving new sync message. The filtered deviation means how
much the system clock was really adjusted. Filtering takes care
of small errors in sync messages.
Auto-lag/lead
The device synchronizes to the sync source, meaning it starts
automatically leading or lagging to stay in perfect sync with the
master. The learning process takes few days.