Toshiba TLP411E, Техническое учебное пособие

Страница: 29 / 84

5-5
3. POWER SUPPLY RESET
PROCESS
In the power supply reset process, a watch dog timer
(MM1096BS) is used as a power supply reset IC (QL04)
as shown in Fig. 5-1.
The reset IC (QL04) accepts a clock pulse signal for the
watch dog timer which is sent from WDT terminal of the
microcomputer, determines the microcomputer is in an ab-
normal status due to some reason if the clock signal does
not exist for about 1s , and sends a reset signal to the RE-
SET terminal of the system microcomputer (QL01).
Fig. 5-2 shows the MN1096BS reset timing diagram.
Fig. 5-3 Non-volatile memory timing diagram
4. NON-VOLATILE MEMORY
PROCESS
In the non-volatile memory process, data reading and writ-
ing for various adjustments are carried out on the non-vola-
tile memory (QL03: CAT24C16) as shown in Fig. 5-1.
When the power (AC) is on, all the adjustment data are
read out by the system microcomputer (QL01) at the tim-
ing shown in the read out timing diagram of Fig. 5-3 (A),
thereby realizing the previous status.
When saving the data, all the adjustment data are written
by the system microcomputer (QL01) at the timing shown
in the timing diagram of Fig. 5-3 (B), thereby keeping the
current status.
However, if a failure (such as power interruption due to
lightening, etc.) occurs during the adjustment data writing,
a data error may occur. If the data is determined as incor-
rect, the initial data memorized on the system microcom-
puter (QL01) is read out and stored on the non-volatile
memory.
Fig. 5-2 MM1096BS reset timing diagram
1s
10 ms 2 ms 10 ms
+5V
+5V
V
CC
CK
RESET
RESET
CS
CLK
DI
DO
Reading mode
Reading mode
H
L
1 2 8 16 24 32
D0 D7 D8 D9 D15
1 0 1 0 1 0 0 0 A0 A1 0 0
RESET
CS
CLK
DI
DO
H
L
1 2 8 16 24 32
D0 D7 D8 D9 D15
1 0 1 0 1 0 0 0 A0 A1 0 0
Address
Address Writing data
Reading data
(A) Reading timing diagram
(B) Writing timing diagram