Toshiba TLP411E, Техническое учебное пособие

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6-13
2-6. Memory Control and Sync Process IC
TC160G54AF1137 (usually called SYG, QX32) is an gate
array which carries out the memory control and sync pro-
cess. SYG is entirely composed of 4 sections as shown in
Fig. 6-16; write timing generation section, read timing gen-
eration section, sync signal measurement section and se-
rial bus interface section.
In the write timing generation circuit, the clock signal in-
put to pin 149 is divided and HD signal for PLL (1) is gen-
erated at pin 128. In the PLL (1), the signal and HD signal
sent from external circuit are compared and a clock signal
synchronized with the input signal is generated. PLL (1)
loop circuit is formed by returning the clock signal to the
write timing circuit through pin 149 after divided in four.
Also, in the write timing circuit, write control signal for a
memory is generated.
In the read timing generation circuit, the memory read con-
trol signal and the reference timing signal for on-screen
generation circuit and liquid crystal panel timing genera-
tion circuit are generated.
A clock signal used in the memory read timing control cir-
cuit operation can be used by switching the clock signal
generated in the PLL circuit (1) (divided in four) and the
clock signal generated in PLL circuit (2) with the serial
bus setting.
When a signal is sent from a personal computer, the clock
signal from PLL circuit (1) is used and when a NTSC/PAL
signal is sent, the clock signal from PLL circuit (2) is used.
In the sync signal measurement section, a HD signal fre-
quency input to pin 134 and line number for 1 field is mea-
sured. The measured data is read to the microcomputer
through the serial bus and used for the personal computer
signal automatic identification. For the measurement ref-
erence signal, 25.18 MHz clock signal is used.
In the serial bus interface section, the data transmission
between the IC and the microcomputer is carried out. The
serial bus format is of a three line bus type using R/W
(pin 44), DATA (pin 43) and CLOCK (pin 42). For the
serial bus format system, refer to item 12 in section 5.
Fig. 6-16 TC160G54AF1137
VDIN (135)
PLLHD (128)
HDIN (134)
OSC2I (81)
Memory writing timing Memory reading timing
(Including HD/VD for OSD, LCD drive)
Timing generation
circuit
Timing generation
circuit
Writing side counter Reading side counter
Sync. phase
control circuit
Clock selector
switch
Sync.
frequency
measurement
circuit/
OSC circuit
Serial bus control circuit
PLL 1 circuit
1/4 divider circuit
Microcomputer
Serial bus
NCODCK
(17)
CLK1l (149)
25.18 MHz
From
PLL 2 circuit