Toshiba TLP411E, Техническое учебное пособие

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7-5
3. VIDEO DEMODULATION
BLOCK
3-1. YC Separation Circuit
This circuit separates Y and C signals from a composite
video signal. Fig. 7-4 shows the pin configuration of
TC9090AN and Fig. 7-5 shows the block diagram.
The composite video signal enters pin 3. A fsc (3.58/
4.43MHz) output from the video/color IC enters pin 19 and
is converted into a 4fsc of the drive clock frequency inside
the IC. The composite video signal entered is processed at
a rate of the clock frequency of the IC and output as Y and
C signal.
Pin
No.
Name Function
1 V
REFL
ADC bias
2 V
SS1
ADC GND
3 ADIN Video input
4 V
DD1
ADC V
DD
5 V
REFH
ADC bias
6 BIAS1 ADC bias
7 P/S Selection function control
8 SCL I
2
C bus clock input
9 SDA I
2
C bus data input, check output
10 RESET I
2
C bus reset
11 TEST1 Test terminal
12 TEST2 Test terminal
13 KILLER Clock killer switch
14 PLLSEL Selection input clock
15 V
DD3
Digital V
DD
16 V
SS3
Analog GND
17 V
SS2
PLL GND
18 V
DD2
PLL V
DD
19 CKIN Clock input
20 VFIL VCO filter
21 2/1 V
DD
Line memory bias
22 BIAS3 DAC bias
23 C
OUT
C output
24 BIAS2 DAC bias
25 Y
OUT
Y output
26 V
REF1
DAC bias
27 V
DD4
DAC V
DD
28 V
SS4
DAC GND
Fig. 7-4 Pin configuration of TC9090AN
Table 7-1 Terminal function of TC9090AN
Fig. 7-5 Block diagram of TC9090AN
2
+ +
25
23
19
8 9
ADC
CLAMP
LINE
MEMORY
VERTICAL EDGE
ENHANCE CIRCUIT
CORING
CIRCUIT
PEDESTAL
CLIP
YDAC
Y
output
C
output
CDAC
8 BIT
COLOR KILLER CIRCUIT
BPF
4.43 MHz NTSC
BPF
BPF
BPF
DYNAMIC
COMB
FILTER
1 LINE DOT
IMPROVE
CIRCUIT
BPF
I
2
C BUS
Bus
4 FSC PLL
Clock
Composite
video signsl
8 BIT
8 BIT
1
2
4
28
27
26
25
3
5 24
6 23
7 22
8 21
9 20
10 19
11 18
12 17
13 16
14 15
V
SS4
V
DD4
V
REF1
Y
OUT
BIAS2
C
OUT
BIAS3
2/1V
DD
VFIL
CKIN
V
DD2
V
SS2
V
SS3
V
DD3
V
REFH
V
SS1
ADIN
V
DD1
V
REFL
BIAS1
P/S
SDA
SCL
RESET
TEST1
TEST2
KILLER
PLLSEL