Toshiba TLP411E, Техническое учебное пособие

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6-9
2-4. PLD Circuit
EPM7032LC44-10 is used for PLD (QX41). This PLD is
based on CMOS EE-PROM and a device which can be
written and erased electrically. The block diagram of the
circuit written in the IC is shown in Fig. 6-11 and its pin
configuration is shown in table 6-5. The IC is composed of
the divider circuit, which operates PLL circuit (2), and
memory control circuit.
In the divider circuit, the clock signal divided in four is
output in the standard mode (including PAL/SECAM mode,
pin 43 (MAG) develops high) and the clock signal divided
in five is output in the enlargement mode (NTSC).
In PLL circuit (2), a clock signal dividing the clock signal
generated in PLL circuit (1), in eight is input to the other
end of an input terminal, so the clock signal with twice
frequency is generated in the standard mode and the clock
signal with 2.5 times frequency is generated in the enlarge-
ment mode.
In the memory control circuit, the memory read operation
is controlled. The control method of the memory is shown
in Fig. 6-12. The RR (read reset) signal for a field shown in
the input signal section in Fig. 6-12 and the RE signal out-
put once 1H are also input from SYG. (The RE signal stands
for read enable signal originally, however, it is regarded as
a HD signal for this unit.)
These signals of clock signal for read (pin 43), enlarge-
ment control signal (pin 44) and field ID signal (pin 2) con-
trol the memory are shown in Fig. 6-12.
In the standard mode, after resetting the memory, the line
increment reset and line hold operations are carried out al-
ternately.
When the line hold operation is carried out, the same line
is read twice repeatedly, so it is possible to convert the
interlace signal into non-interlace signal. The line being
read twice repeatedly is changed by ODD/EVEN of the
field in order to correct the center of the interlace signal.
In the enlargement mode, after resetting the memory, the
line hold operation once between the line increment opera-
tions and the line hold operation twice between the line
increment operations are carried out alternately.
The operation is equivalent to convert one line into 2.5 lines,
because the same line is read repeatedly twice and three
times alternately. In this operation, twice conversion of the
non-interlace signal conversion is included, so the picture
is enlarged 1.25 times in the vertical direction. In this case,
the operation pattern is also shifted by 1 line by the ODD/
EVEN of a field to perform the center correction for the
interlace signal. In this kind of conversion, shaggy lines
may be conspicuous at a slanted portion because a line is
simply enlarged repeatedly.
Pin 4 (CLR) controls all output terminals of the PLD to
low. When a signal comes from a personal computer, this
terminal is set to Hi to stop the PLD operation.
Fig. 6-11 EPM7032LC44-10 internal block diagram
40 NRLRS
ORCK
Vcc
GND
Vcc
GND
Vcc
GND
NRRS
GND
IRCK
FIOE
Vcc
CLR
NRE
NRR
MAG
41
42
43
44
1
2
3
4
5
6
28
27
26
25
24
23
22
21
20
19
18
7 8 9 10 11 12 13 14 15 16 17
39 38 37 36 35 34 33 32 31 30 29
MEMORY
TIMING
CONTROL
4
5
Table 6-5 EPM7032LC44-10 pin function
Pin
No.
Name Functions
2 FIOE
Field ODD/EVEN ID signal (ODD:
Lo)
4 CLR
Output clear input terminal (All
outputs become Lo when Hi.)
5 NRE
RE (Read Enable) signal input
terminal
6 NRR
RR (Read Reset) signal input
terminal
24 ORCK Clock output terminal (PLL (2))
40 NRLRS
RLRS (Read Line Reset) signal
output terminal
41 NRRS
RRS (Read Reset) signal output
terminal
43 IRCK Clock input terminal
44 MAG
Enlargement control signal output
terminal