7-6
(19) Pin 19 is H.LOCK output terminal.
This model does not use this terminal. This terminal gives
output of discriminating result of approx. 5V, when hor sync
signal input from outside of IC and hor output at pin16 are in
synchronization.
(22) Pin 22
Capacitor for producing AFC comparing wave is connected.
The external capacitor is selected so that triangle waveform
at pin22 becomes approx. 2 to 3V. If wave height is small,
the loop-gain of AFC decreases.
5.7V
1.5K
500
19
Fig. 18
(20) Pin 20
FBP which is input from pin18, is delayed by the time
constant of this pin.
920U
MAX
22
100
30
5K
3300pF
Fig. 20
(23) Pin 23 is GND terminal of Ver block.
(24) Pin 24 is ver output terminal.
The output voltage is approx. 5V when the terminal is set in
high impedance. And output current becomes approx. 2mA
when the terminal is connected to ground through 100 ohm.
Internal transistor can accept current of approx. 10mA.
HIGH period of output is 300 µs, and it is independent of
frequency of ver sync signal which is input at pin 30. By the
control voltage of pin 26; V SHIFT terminal, the rising of this
pin voltage can be delayed by approx. 0 to 470 µs against the
front edge of ver sync signal.
0.5V
2K
10
24
50K
Fig. 21
100
150pF
100
20
22K
Fig. 19
(21) Pin 21 is a terminal for power source of the ver block.
The rated voltage is 12V.
Содержание MM20E45
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