Toshiba MM20E45, Техническое учебное пособие

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2-1
SECTION II CHANNEL SELECTION CIRCUIT
1. OUTLINE OF CHANNEL SELECTION
SYSTEM
The channel selection circuit in the N5MM1 chassis employs
a bus system which performs a central control by connecting
a channel selection microcomputer to a control IC in each
circuit block through control lines called a bus.
In the bus system which controls each IC, the I
2
C-bus system
(two line bus system) promoted by Philips Co., Ltd. in the
Netherlands has been employed.
The ICs controlled by the I
2
C-bus control system are: ICG01
for audio system process, ICA02 for non-volatile memory,
H001 for main U/V tuners, IC302 for deflection distortion
corrections.
2. OPERATION OF THE CHANNEL
SELECTION CIRCUIT
2-1 Channel Selection Control Microcomputer
(ICA01 Toshiba TMP87CM34N-3101)
8 bit microcomputer, TLCS-870 series for TV receivers,
TMP87CM34N (42 pins, built-in CCD) developed by Toshiba
is employed. With this microcomputer each IC and circuit
shown below are controlled.
2-1-1 Non-volatile Memory IC
(ICA02 NEC µPD672CX)
(1) Memorizes data for video and audio signal adjustment
values, sound volume, woofer adjustment value, external
input status, etc.
(2) Memorizes adjustment data for white balance (RGB cut
off, GB drive), sub-brightness, sub color, sub-tint, etc.
(3) Memorizes deflection distortion correction value data
adjusted for each unit.
2-1-2 U/V Tuner Unit
(H001 Toshiba EL911L)
(1) A desired station can be received by transferring a
channel selection frequency data (division data) to the
I
2
C-bus type frequency synthesizer provided in the
tuner and by setting a band switch data which selects the
UHF or VHF band.
2-1-3 Deflection Distortion Correction IC
(IC302 Toshiba TA8859AP)
(1) Sets adjustment memory values for vertical amplitude,
linearity, horizontal amplitude, parabola, corner, pedestal
distortion, etc.
2-1-4 Audio System Process IC
(ICG01, SONY CXA1784S)