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Programmable Hardware Manual (PHM)
© Tibbo Technology Inc.
In the smart LED configuration, the FPGA receives the data from the CPU through
the SPI interface and stores this data in the 8192-byte data buffer.
As with all SPI communications, transactions start when the -CS line goes LOW and
end when the -CS line goes HIGH. Bringing the -CS line LOW clears the memory
buffer of the FPGA and resets the buffer pointer to 0 (first buffer location). Each
subsequent byte of data sent in the course of an SPI transaction is stored into the
buffer location pointed at by the buffer, and then the pointer is incremented by one.
Once the -CS line goes HIGH, the FPGA starts sending the data stored in its buffer
memory to the LED chain.
The DONE signal (which is multiplexed with the MISO line) is asserted LOW for the
duration of the LED update cycle, meaning that DONE goes LOW as soon as -CS
goes HIGH. The DONE signal goes HIGH once the LED update cycle is completed. To
query the state of the DONE signal, read the DONE/MISO line while the -CS is HIGH.
New SPI transaction should not start while the DONE signal is LOW.
Data format for SPI write transactions
Byte number
MOSI
MISO
1
Green level, LED N*
---
2
Red level, LED N
---
3
Blue level, LED N
---
4
White level, LED N
---
5
Green level, LED N-1
---
6
Red level, LED N-1
---
7
Blue level, LED N-1
---
8
White level, LED N-1
---
---
---
---
Green level, LED 2
---
Red level, LED 2
---
Blue level, LED 2
---
White level, LED 2
---
Green level, LED 1
---
Red level, LED 1
---
