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Programmable Hardware Manual (PHM)
© Tibbo Technology Inc.
stored into the
. The length of the recorded data (in bytes) can be
obtained from the
After the Tibbit receives the command to record the data, it starts waiting for the
first "IR light ON" state. The end of data is detected using a timeout method. After
the recording ends, bit 0 of the
is set to 1. Therefore, your program
can poll this bit to determine when the data is ready (and if anything was received
at all).
IR receivers vary in how they output "IR light ON" (detected) and "IR light OFF" (not
detected) states. Many receivers output HIGH when the IR light is OFF, and LOW
when it is ON. We refer to such output lines as "normal". Some receivers are doing
this in reverse, meaning that LOW corresponds to the absence of the IR light, and
HIGH corresponds to the presence of the IR light. We refer to such output lines as
"inverted". Option bit 2 of the
allows you to set the type of the
attached IR receiver.
When storing the recorded IR signal, remember to preserve not only the data from
the
(in the length determined by the
), but also the
divider value from the
.
Outgoing IR streams
Your program shall prepare the data for the output IR stream in the
The format of data is the same wit the RX data buffer. Note that RX and TX buffers
are physically separate so if you want to immediately play back the signal you've
just recorded you still need to copy the data from the RX buffer into the TX buffer.
Prior to sending the "start transmitting data"
the
. As explained above, the information about the
modulation frequency should be stored along with the IR data itself.
IR emitters vary in the polarity of their control signal. Many emitters turn their IR
LED on when the control line is LOW. We refer to such control lines as "normal".
Some emitters turn their IR LED on when the control line is HIGH. We call this an
inverted control line. Option bit 3 of the
type of the attached IR emitter.
Resetting and Initializing the Onboard FPGA
For correct operation, the FPGA IC must be properly reset and uploaded with the
run-time binary code. Since
only have four CPU lines, implementing a
dedicated reset line wasn't possible. As a result, FPGA reset is generated by
manipulating -CS and SCLK lines.
Here is the FPGA reset procedure (for reference, see
tbt26_init()
@
tbt26.tbs
of the
test_tibbit_26 project
):
·
Set the -CS line HIGH.
·
Set the SCLK line LOW.
·
Set the SCLK line HIGH. Now the FPGA is in reset.
·
Generate a small delay (optional).
·
Set the -CS line LOW.
·
Set the SCLK line LOW.