376
Tibbo Project System (TPS)
© Tibbo Technology Inc.
from reset, you need to set the -CS line LOW and produce another rising edge on
the SCLK line.
Once the FPGA is out of reset, avoid toggling the SCLK line while the -CS is HIGH
(inactive). This shouldn't be problematic as there is no point in generating SPI
clocks while the chip select is not asserted.
Following reset, the FPGA must be uploaded with the run-time binary file (for
reference, see
tbt57_init()
@
tbt57_common.tbs
of the
test_tibbit_57_sled
project
). What binary file is to be uploaded depends on the desired FPGA function.
The full list of available configurations is found in
Key points:
·
SPI mode 2 is used; bytes are transmitted MSBit first.
·
Bytes of the run-time binary (
IR_Remote_bitmap.bin
) are sent to the FPGA one
after one.
·
After the last byte has been sent, the program generates 50 additional clock
cycles. We don't know why this is necessary. We just followed Lattice
specification.
·
After that, the success or failure of the upload procedure are verified through the
DONE/MISO line.
As the name implies, the DONE/MISO line serves two functions. When the -CS is
asserted (LOW), this line works as the standard MISO line of the SPI interface.
When the -CS line is HIGH, this line channels the state of the FPGA's CDONE output.
This output becomes HIGH if the upload of the binary file was successful.
Implemented Configurations
At the moment there is only one use for the FPGA Tibbit:
·
Smart LED Controller Configuration
Smart LED Controller Configuration
In the smart LED configuration, Tibbit #57 can control a string of daisy-chained
SK6812RGBW LEDs. SK6812RGBW devices carry a small IC driving four onboard light
emitters with red, green, blue, and white colors. Each of the color sources can be
set to one of the 256 levels of brightness, meaning that four bytes of data are
needed per LED.
Smart LEDs are controlled via a special 1-wire protocol. Each LED has a DIN (data
in) and DOUT (data out) pins. The DIN pin of the first LED in the chain is connected
to the IO1 line of the FPGA Tibbit. The DOUT of the first LED is connected to the
DIN of the second LED, the DOUT of the second LED -- to the DIN of the third LED,
and so on.