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Programmable Hardware Manual (PHM)
© Tibbo Technology Inc.
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Once the TFS line goes HIGH marking the end of the write transaction, the DI line
starts indicating the status of the converter.
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The DI line will be HIGH while the converter is still busy.
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The DI line will become LOW when the calibration is finished.
There is no need to set MD2-0= 000 after the calibration -- this happens
automatically. So, in effect, your entire A/D converter setup may consist of writing
22004E Hex (or other suitable configuration word) and waiting for the DI to become
LOW.
Changing channels
Follow these steps to change the channel:
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If the desired channel is not selected yet, select it by manipulating control lines
CHS2-0. Code 000 selects the channel 1, 001- channel 2, ... 111- channel 8.
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After the channel change, discard the results of the first conversion. This is
because the channel change may result in the wrong measurement. The second
measurement will contain correct data. Alternatively, your program can wait the
time equal to two A/D measurement periods. Conversion period is related to the
filter setting. For the filter set at 250Hz, the conversion period is 1/250Hz=4ms.
So, the application needs to wait for 8ms before correct data for the newly
selected channel becomes available.
Receiving A/D conversion result
The data register of the A/D converter is updated at the conversion rate (for our
recommended setting, 1/250Hz=4ms). So, the new measurement result is available
every 4ms. You are always reading the most recent conversion result.
The readout can only start when the A/D converter is ready. Starting the read
transaction when the converter is not ready will produce invalid data (you will read
"all zeroes" or "all ones"). Follow this algorithm to perform the read:
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While the RFS line is at HIGH, read the state of the DI line. If the line is HIGH,
then the A/D converter is not ready and you need to wait.
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Keep polling the DI line until it becomes LOW. This will indicate that the read
transaction can be started.
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Set C/D line HIGH to indicate that the data register access will take place.
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Set the RFS line LOW to indicate that this will be a read operation (TFS must
remain HIGH).
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Set the CLOCK line HIGH and record the state of the DI line -- this is the value of
the most significant bit.
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Set the CLOCK LOW -- this concludes the first clock cycle.
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Perform 23 or 15 more clock cycles (depending on the value you set in the WL bit
of the configuration register), every time recording the state of the DI line when
the CLOCK is it HIGH.
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Set the RFS line HIGH. The read is complete.
Remember that the "effective resolution" discussed above has nothing to do
with the number of bits you are supposed to read from the converter. This
number is either 24 or 16, depending on the WL bit of the configuration
register.