375
Programmable Hardware Manual (PHM)
© Tibbo Technology Inc.
Both non-standard features are described in
Resetting and Initializing the Onboard
.
LEDs
There are three red LEDs and one green LED. These four LEDs are connected to four
interface lines of the Tibbit. LEDs light up for the LOW state of the interface lines.
Red LEDs are connected to the -CS, SCLK, and MOSI lines. The green LED is
connected to the DONE/MISO line.
Sample project
The use of this Tibbit is illustrated by a Tibbo BASIC test project. Yo can find it
here:
https://github.com/tibbotech/CA-Test-Tibbit-57
Further info
Resetting and initializing the onboard FPGA
Resetting and Initializing the Onboard FPGA
For correct operation, the FPGA IC must be properly reset and uploaded with the
run-time binary code. Since
only have four CPU lines, implementing a
dedicated reset line wasn't possible. As a result, FPGA reset is generated by
manipulating -CS and SCLK lines.
Here is the FPGA reset procedure (for reference, see
tbt57_init()
@
tbt57_common.tbs
of the
test_tibbit_57_sled project
):
·
Set the -CS line HIGH.
·
Set the SCLK line LOW.
·
Set the SCLK line HIGH. Now the FPGA is in reset.
·
Generate a small delay (optional).
·
Set the -CS line LOW.
·
Set the SCLK line LOW.
·
Set the SCLK line HIGH. Now the FPGA is out of reset.
If the above sounds cryptic, here is the schematic diagram of the reset circuit:
The circuit is based on a D trigger that is clocked by the SCLK line. The data input D
of the trigger is connected to the -CS line. The FPGA's reset line (active LOW) is
taken from the inverted output -Q of the trigger. Setting the -CS line HIGH and
producing a rising edge on the SCLK line latches the trigger, and its -Q (inverted)
output becomes LOW. The FPGA IC enters the reset state. To release the FPGA