Texas Instruments TRF7963A, Руководство пользователя

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Slave
Select
MISO
MOSI
Data
Clock
Write Mode
CKPH = 1, CKPL = 0
Data Transition is on
Data Clock Falling Edge
MOSI Valid on Data Clock Rising Edge
t
STE,LEAD
t
STE,LAG
b7
t
LO/HI
t
LO/HI
b6 to b1 b0
t
SU,SI
t
HD,SI
1/f
UCxCLK
b0
b6... ...b1 b7
Don't Care
No Data Transitions
(All High, Low)
Switch
DATA_CLK
Polarity
Read Mode
CKPH = 0, CKPL = 0
Data Transition is on
Data Clock Rising Edge
MOSI Valid on Data Clock Falling Edge
t
STE,LAG
t
SU,SO
t
HD,SO
t
VALID,SO
t
STE,DIS
50 ns
Start
Condition
Stop
Condition
b7 b6 b5 b4 b3 b2 b1 b0
Data Clock
Data In
Data Out
33
TRF7963A
www.ti.com SLOS758G – DECEMBER 2011 – REVISED MARCH 2020
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Detailed Description
Copyright © 2011–2020, Texas Instruments Incorporated
Figure 6-16. SPI Without Slave Select Timing
In this mode, a rising edge on data in (I/O_7, pin 24) while SCLK is high resets the serial interface and
prepares it to receive data. Data in can change only when SCLK is low, and it is read by the reader on the
SCLK rising edge. Communication is terminated by the stop condition when the data in falling edge occurs
during a high SCLK period.
6.12.6.2 Serial Interface Mode With Slave Select (SS)
The serial interface is in reset while the Slave Select signal is high. Serial data in (MOSI) changes on the
falling edge and is validated in the reader on the rising edge (see
Figure 6-17 ). Communication is
terminated when the Slave Select signal goes high.
All words must be 8 bits long with the MSB transmitted first.
Figure 6-17. SPI With Slave Select Timing
The read command is sent out on the MOSI pin, MSB first, in the first eight clock cycles. MOSI data
changes on the falling edge, and is validated in the reader on the rising edge, as shown in
Figure 6-17 .
During the write cycle, the serial data out (MISO) is not valid. After the last read command bit (B0) is
validated at the eighth rising edge of SCLK, after half a clock cycle, valid data can be read on the MISO
pin at the falling edge of SCLK. It takes eight clock edges to read out the full byte (MSB first).
When using the hardware SPI (for example, an MSP430 hardware SPI) to implement this feature, care
must be taken to switch the SCLK polarity after write phase for proper read operation. The example clock
polarity for the
Figure 6-17 shows the MSP430-specific environment in the write-mode and read-mode
boxes. See the USART-SPI chapter for any specific microcontroller family for further information on the
setting the appropriate clock polarity. This clock polarity switch must be done for all read (single or
continuous) operations. The MOSI (serial data out) should not have any transitions (all high or all low)
during the read cycle. The Slave Select should be low during the whole write and read operation.
See Section 5.6 , Switching Characteristics , for the timing values shown in Figure 6-17 .
Figure 6-18 shows the continuous read operation.