Texas Instruments TRF7963A, Руководство пользователя

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TRF7963A
www.ti.com SLOS758G – DECEMBER 2011 – REVISED MARCH 2020
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Detailed Description
Copyright © 2011–2020, Texas Instruments Incorporated
6.14.1.3.2 Collision Position and Interrupt Mask Registers (0x0D and 0x0E)
Table 6-32 describes the bit fields of the Collision Position and Interrupt Mask register.
Default Value: 0x3E, set at POR = H and EN = L. Collision bits reset automatically after read operation.
Table 6-32. Collision Position and Interrupt Mask Register (0x0D)
BIT NO. BIT NAME FUNCTION DESCRIPTION
B7 Col9 Bit position of collision MSB Supports ISO/IEC 14443 A
B6 Col8 Bit position of collision
B5 En_irq_fifo Interrupt enable for FIFO Default = 1
B4 En_irq_err1 Interrupt enable for CRC Default = 1
B3 En_irq_err2 Interrupt enable for Parity Default = 1
B2 En_irq_err3
Interrupt enable for Framing
error or EOF
Default = 1
B1 En_irq_col Interrupt enable for collision error Default = 1
B0 En_irq_noresp Enables no response interrupt Default = 0
Table 6-33 describes the bit fields of the Collision Position register. This register displays the bit position of
collision or error.
Default Value: 0x00, set at POR = H and EN = L. The register is also automatically reset after a read.
Table 6-33. Collision Position Register (0x0E)
BIT NO. BIT NAME FUNCTION DESCRIPTION
B7 Col7
Bit position of collision. B7 is the
MSB.
ISO/IEC 14443 A mainly supported; in the other protocols, this
register shows the bit position of error. Either frame, SOF/EOF,
parity, or CRC error.
B6 Col6
B5 Col5
B4 Col4
B3 Col3
B2 Col2
B1 Col1
B0 Col0