CLK
I/O_[7]
I/O_[6:0]
a0 [7]
d0 [7]
d1 [7]
d2 [7]
d3 [7]
dN [7]
a0 [6:0]
d0 [6:0]
d1 [6:0]
d2 [6:0]
d3 [6:0]
dN [6:0]
xx
xx
50 ns
Start
Condition
StopCont
Continuous Mode
CLK
I/O_[7]
I/O_[6:0]
a1 [7]
d1 [7]
a2 [7]
d2 [7]
aN [7]
dN [7]
a1 [6:0]
d1 [6:0]
a2 [6:0]
d2 [6:0]
aN [6:0]
dN [6:0]
50 ns
Start
Condition
StopSmpl
Condition
30
SLOS758G – DECEMBER 2011 – REVISED MARCH 2020
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Detailed Description
Copyright © 2011–2020, Texas Instruments Incorporated
Figure 6-11. Parallel Interface Communication With Simple Stop Condition (StopSmpl)
Figure 6-12. Parallel Interface Communication With Continuous Stop Condition (StopCont)
Figure 6-13. Parallel Interface Communication With Continuous Stop Condition
6.12.4 Reception of Air Interface Data
At the start of a receive operation (when SOF is successfully detected), B6 is set in the IRQ Status
register. An interrupt request is sent to the MCU at the end of the receive operation if the receive data
string was shorter than or equal to 8 bytes. The MCU receives the interrupt request, then checks to
determine the reason for the interrupt by reading the IRQ Status register (address 0x0C), after which the
MCU reads the data from the FIFO.
If the received packet is longer than 8 bytes, the interrupt is sent before the end of the receive operation
when the ninth byte is loaded into the FIFO (75% full). The MCU must read the FIFO status register
(0x1C) to determine the number of bytes to be read from the FIFO. Next, the MCU must read the data in
the FIFO. It is optional but recommended to read the FIFO Status register (0x1C) after reading the FIFO
data to determine if the receive is complete. In the case of an IRQ_FIFO, the MCU should expect either
another IRQ_FIFO or RX complete interrupt. This is repeated until an RX complete interrupt is generated.
If the reader detects a receive error, the corresponding error flag is set (framing error, CRC error) in the
IRQ Status register, indicating to the MCU that reception was not completed correctly.
