Texas Instruments TPS65917-Q1, Техническое справочное руководство

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2 SLVUAH1C – June 2015 – Revised April 2017
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Copyright © 2015–2017, Texas Instruments Incorporated
Introduction
Chapter 1
SLVUAH1C – June 2015 – Revised April 2017
Introduction
This document presents a summary of the hardware interface for the TPS65917-Q1 device. Each module
instance within the design is shown along with the module register map and bit definitions for each bitfield.
1.1 Register Address Mapping
This document describes the register mapping of the TPS65917-Q1 device. The operation of the IC is
described in the device data sheet,
TPS65917-Q1 Power Management Unit (PMU) for Processor .
The 3 hex digits of the physical address of the register indicated in this document are mapped as 0xPAA,
while P stands for the page number of the register, and AA stands for the register address within the
memory page. The page numbers are mapped to the slave device address as following:
Page = 0x0 — Slave Device address 0x12 for DVS registers
Page = 0x1 — Slave Device address 0x48 or 0x58 for Power registers
Page = 0x2 — Slave Device address 0x49 or 0x59 for Interfaces and Auxiliaries registers
Page = 0x3 — Slave Device address 0x4A or 0x5A for Trimming and Test registers
Page = 0x4 — Slave Device address 0x4B or 0x5B for OTP programming registers
For the reset of the registers, the registers are defined by 3 categories:
• POR: Power On Reset registers
• HWRST: Hardware Reset registers
• SWORST: Switch Off Reset registers
These categories of registers (POR, HWRST, SWORST) are described in the device data sheet. When
the reset value of a bit register is 0bX, it means the bit value is coming from the OTP memory.
NOTE: All reserved bits are read only (R). Read to an unmapped register returns previous read
value.