6.1
PLL Controller Module
SPRUFB3 – September 2007
PLL Controllers (PLLCs)
The DM355 has two PLL controllers that provide clocks to different components of the chip. PLL controller
1 (PLLC1) provides clocks to most of the components of the chip. PLL controller 2 (PLLC2) provides
clocks to the DDR PHY.
As a module, the PLL controller provides the following:
•
Glitch-free transitions (on changing PLL settings)
•
Domain clocks alignment
•
Clock gating
•
PLL bypass
•
PLL power down
The various clock outputs given by the PLL controller are as follows:
•
Domain clocks: SYSCLKn
•
Bypass domain clock: SYSCLKBP
•
Auxiliary clock from reference clock: AUXCLK
Various dividers that can be used are as follows:
•
Pre-PLL divider: PREDIV
•
Post-PLL divider: POSTDIV
•
SYSCLK divider: PLLDIV1,
…
, PLLDIVn
•
SYSCLKBP divider: BPDIV
Multipliers supported are as follows:
•
PLL multiplier control: PLLM
38
PLL Controllers (PLLCs)
SPRUFB3 – September 2007
