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9.10.19 VPSS_CLK_CTRL - VPSS Clock Mux Control
System Control Register Descriptions
The VPSS Clock multiplexing control is provided by the VPSS_CLK_CTRL register.
Figure 9-18. VPSS_CLK_CTRL - VPSS Clock Mux Control
31
16
RESERVED
R-0
15
8
RESERVED
R-0
7
6
5
4
3
2
1
0
RESERVED
VENC_CLK_SRC
DACCLKEN
VENCLKEN
PCLK_INV
VPSS_MUXSEL
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-21. VPSS_CLK_CTRL - VPSS Clock Mux Control Field Descriptions
Bit
Field
Value
Description
31-7
RESERVED
Reserved
6-5
VENC_CLK_SRC
27MHz Input Source
0
PLL1 divided down (SYSCLK3)
1
External crystal 2 (MXI2/MXO2)
2
External crystal 1 (MXI1/MXO1)
3
RESV
4
DACCLKEN
Enable Video DAC clock
0
disable
1
enable
3
VENCLKEN
Enable VPBE/Video Encoder clock
0
disable
1
enable
2
PCLK_INV
Invert VPFE pixel clock (PCLK)
0
VENC clk mux and CCDC receive normal PCLK
1
VENC clk mux and CCDC receive inverted PCLK
1-0
VPSS_MUXSEL
VPSS clock selection
0
Use clock from PLL1 SYSCLK3, MXI2, or MXI1. Selection is determined by bit VENC_CLK_SRC.
(DAC clock = selected clock: PLL1 SYSCLK3, MXI2, or MXI1 )
1
RESV
2
Use external VPBE clock input, EXTCLK pin (DAC clock = EXTCLK)
3
Use pxiel clock from VPFE, PCLK pin (DAC clock = off)
SPRUFB3 – September 2007
System Control Module
141