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9.10.7 BOOTCFG - Boot Configuration
System Control Register Descriptions
The device boot configuration (the state of the BTSEL[1:0] and AECFG[3:0] signals are captured in the
BOOTCFG register).
Figure 9-6. BOOTCFG - Boot Configuration
31
16
RESERVED
R-0
15
9
8
RESERVED
GIO0_RESET
R-0
R-0
7
6
5
4
3
0
BTSEL
RESERVED
AECFG
R-0
R-0
R-1101
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-9. BOOTCFG - Boot Configuration Field Descriptions
Bit
Field
Value
Description
31-9
RESERVED
Reserved
8
GIO0_RESET
GIO0 Value Sampled at Reset Sampled prior to debounce circuit
7-6
BTSEL
Configuration at boot of BTSEL[1:0] pins
Take care that AECFG[3:0] settings, which configure AEMIF pin mux settings in PINMUX2[4:0], are
compatible with the boot mode:
- OneNAND boot requires AECFG[3:0] = 0010b
- Only 8_bit NAND boot is supported - AECFG[3:0] = 1XXXb
0
Boot from ROM - NAND Flash boot mode
1
Boot from AEMIF - OneNAND
2
Boot from ROM - SD0 boot mode
3
Boot from ROM - UART0 boot mode
5-4
RESERVED
Reserved
3-0
AECFG
AEMIF Configuration settings for boot by AECFG[3:0] pins
[3] - AEMIF Data Bus width (0 = 16-bit, 1 = 8-bit)
[2:1] - Configuration of EM_AN pin
- 00 = BA0, needed for 8-bit ASYNC memories or devices
- 01 = A[14], required for OneNAND operation and AEMIF in Half_Rate mode
- 10 = GIO[54], usable in NAND mode only
- 11 = reserved
[0] - AEMIF Address bus width (0 = A{13:3] and A[0], BA1
Take care that AECFG[3:0] settings, which configure AEMIF pin mux settings in PINMUX2[4:0], are
compatible with the boot mode:
- OneNAND boot requires AECFG[3:0] = 0010b
- Only 8_bit NAND boot is supported _ AECFG[3:0] = 1XXXb
128
System Control Module
SPRUFB3 – September 2007