follower mode), but the standard measurement loop does not restart until the next 1-s boundary occurs within
the device timing. Therefore, new data may not be available for up to ≈1 s after the device exits SLEEP mode.
The coulomb counter ADC operates in a reduced power and speed mode to monitor current during SLEEP
mode. The current is measured every 12 ms and, if it exceeds a programmable threshold in magnitude, the
device quickly transitions back to NORMAL mode. In addition to this check, if CC1 Current measurement taken
at each programmed interval exceeds this threshold, the device exits SLEEP mode.
The device monitors the PACK pin voltage and the top-of-stack voltage at each programmed measurement
interval. If the PACK pin voltage is higher than the top-of-stack voltage by more than a programmable delta
and the top-of-stack voltage is less than a programmed threshold, the device exits SLEEP mode. The BQ76942
device also includes a hysteresis on the SLEEP mode entrance to avoid the device quickly entering and exiting
SLEEP mode based on a dynamic load. After transitioning to NORMAL mode, the device will not enter SLEEP
mode again for a number of seconds given by the hysteresis setting.
During SLEEP mode, the DSG FET can be driven either using the charge pump or in source-follower mode (as
described in
). The CHG FET can be disabled or driven using the charge pump, based
on the configuration setting.
13.4 DEEPSLEEP Mode
The BQ76942 device integrates a DEEPSLEEP mode, which is a low-power mode that allows the REG1 and
REG2 LDOs to remain powered, but disables other subsystems. In this mode, the protection FETs are disabled,
so no voltage is provided at the battery pack terminals. All protections are disabled, and all voltage, current, and
temperature measurements are disabled.
DEEPSLEEP mode can be entered by sending a subcommand over the serial communications interface. The
device exits DEEPSLEEP mode returns to NORMAL mode if directed by a subcommand, or if the RST_SHUT
pin is asserted for < 1-s, or if a charger is attached (which is detected by the voltage on the LD pin rising from
below V
WAKEONLD
to exceed it). In addition, if the BAT pin voltage falls below V
PORA
– V
PORA_HYS
, the device
transitions to SHUTDOWN mode.
When the device exits DEEPSLEEP mode, it first completes a full measurement loop and evaluates conditions
relative to enabled protections to ensure that conditions are acceptable to proceed to NORMAL mode. This may
take ≈250 ms plus the time for the measurement loop to complete.
The REG1 and REG2 LDOs maintain their power state when entering DEEPSLEEP mode based on the
configuration setting. The device also provides the ability to keep the LFO running while in DEEPSLEEP mode,
which enables a faster responsiveness to communications and transition back to NORMAL mode, but consumes
additional power.
Other than sending a subcommand to exit DEEPSLEEP mode, communications with the device over the serial
interface do not cause it to exit DEEPSLEEP mode; however, since no measurements are taken while in
DEEPSLEEP mode, there is no new information available for readout.
13.5 SHUTDOWN Mode
SHUTDOWN mode is the lowest power mode of the BQ76942 device, which can be used for shipping or
long-term storage. In this mode, the device loses all register state information, the internal logic is powered
down, the protection FETs are all disabled, so no voltage is provided at the battery pack terminals. All protections
are disabled, all voltage, current, and temperature measurements are disabled, and no communications are
supported. When the device exits SHUTDOWN, it will boot and read parameters stored in OTP (if that has been
written). If the OTP has not been written, the device will power up with default settings, and then settings can be
changed by the host writing device registers.
Entering SHUTDOWN mode involves a sequence of steps. The sequence can be initiated manually through the
serial communications interface. The device can also be configured to enter SHUTDOWN mode automatically
based on the top of stack voltage or the minimum cell voltage. If the top-of-stack voltage falls below a
programmed stack voltage threshold, or if the minimum cell voltage falls below a programmed cell voltage
threshold, the SHUTDOWN mode sequence is automatically initiated. The shutdown based on cell voltage does
not apply to cell input pins being used to measure interconnect.
SLUSE14B – DECEMBER 2020 – REVISED DECEMBER 2021
Copyright © 2021 Texas Instruments Incorporated
51
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