Texas Instruments BQ76942, Руководство пользователя

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A7 A6 A1
...
R7
R/W
R6 R0
...
D0
...
C7 C6 C0
...
Start
Responder
Address
Register
Address
Stop
SCL
SDA
A7 A6 A1
...
R/W ACK ACK ACK
D7 D6
ACK NACK
Responder
Address
Respsonder
Drives CRC
(optional)
Controller
Drives NACK
Responder
Drives Data
Repeated
Start
Figure 14-2. I
2
C Read with Repeated Start
I
2
C Read without Repeated Start shows a read transaction where a Repeated Start is not used, for example if
not available in hardware. For a block read, the controller ACK’s each data byte except the last and continues to
clock the interface. The I
2
C block will auto-increment the register address after each data byte.
When enabled, the CRC for a read transaction is calculated as follows:
• In a single-byte read transaction, the CRC is calculated beginning at the first start, so will include the
responder address, the register address, then the responder address with read bit set, then the data byte.
• In a block read transaction, the CRC for the first data byte is calculated beginning at the first start and will
include the responder address, the register address, then the responder address with read bit set, then the
data byte. The CRC resets after each data byte and after each stop. The CRC for subsequent data bytes is
calculated over the data byte only.
The CRC polynomial is x
8
+ x
2
+ x + 1, and the initial value is 0.
When the controller detects an invalid CRC, the I
2
C controller will NACK the CRC, which causes the I
2
C
responder to go to an idle state.
A7 A6 A1
...
R7
R/W
R6 R0
...
D0
...
C7 C6 C0
...
Start
Register
Address
Stop
SCL
SDA
A7 A6 A1
...
R/W ACK ACK ACK
D7 D6
ACK NACK
Responder
Drives CRC
(optional)
Controller
Drives NACK
Responder
Drives Data
Stop Start
Responder
Address
Responder
Address
Figure 14-3. I
2
C Read without Repeated Start
14.3 SPI Communications Interface
The SPI interface in the BQ76942 device operates as a responder-only interface with an optional CRC check.
If the OTP has not been programmed, the BQ76942 device will initially power up by default in 400 kHz
I
2
C mode, while other device versions will initially powerup by default in SPI mode with CRC enabled, as
described in the Device Comparison Table . The OTP setting to select SPI mode can be programmed into the
BQ76942 on the manufacturing line, then when the device powers up, it enters SPI mode automatically. The
host can also change the serial communication setting while in CONFIG_UPDATE mode, although the device
will not immediately change communication mode upon exit of CONFIG_UPDATE mode, in order to avoid losing
communications during evaluation or production. The host can reset the device or write the
SWAP_TO_SPI()
subcommand to change the communications interface to SPI immediately.
BQ76942
SLUSE14B – DECEMBER 2020 – REVISED DECEMBER 2021
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