Typical values stated where T
A
= 25°C and V
BAT
= 55.0 V, min/max values stated where T
A
= -40°C to 85°C and V
BAT
= 4.7 V
to 55 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
(CHGFETOFF)
CHG off voltage with
respect to BAT
CHG/DSG C
L
= 20 nF, steady state value
0.4
V
V
(DSGFETOFF)
DSG off voltage with
respect to LD
CHG/DSG C
L
= 20 nF, steady state value
0.7
V
t
(FET_ON)
CHG and DSG rise
time
CHG/DSG C
L
= 20 nF, R
GATE
= 100 Ω, 0.5
V to 4 V gate-source overdrive, charge pump
mode
21
40
µs
t
(CHGFETOFF)
CHG fall time to BAT
CHG C
L
= 20 nF, R
GATE
= 100 Ω, 90% to
10% of V
(FETON)
46
65
µs
t
(DSGFETOFF)
DSG fall time to LD
DSG C
L
= 20 nF, R
GATE
= 100 Ω, 90% to 10%
of V
(FETON)
2
20
µs
t
(CP_START)
Charge pump start up
time
C
L
= 20 nF, C
(CP1)
= 470 nF, 10% to 90% of
V
(FETON)
100
ms
C
(CP1)
Charge pump
capacitor
100
470
2200
nF
(1)
When the DSG driver is enabled, the CHG driver is disabled, and a voltage is applied at the LD pin such that V
LD
> V
DSG
, the voltage
at DSG will rise to ≈ V
LD
- 0.7 V
(2)
Specified by design
(3)
Specified by characterization
(4)
R
GATE
can be optimized during design and system evaluation for best performance. A larger value may be desired to avoid an overly
fast FET turn off, which can result in a large voltage transient due to cell and harness inductance.
7.26 Comparator-Based Protection Subsystem
Typical values stated where T
A
= 25°C and V
BAT
= 55.0 V, min/max values stated where T
A
= -40°C to 85°C and V
BAT
= 4.7 V
to 55 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
(OVP)
Overvoltage detection range
Nominal setting (50.6 mV steps)
1.012 V
to 5.566
V in 50.6
mV steps
V
V
(OVP_ACC)
Overvoltage detection voltage
threshold accuracy
T
A
= +25°C, nominal setting between
±2
mV
T
A
= +25°C, nominal setting between
3.036 V and 5.06 V
–10
10
mV
T
A
= –10°C to +60°C, nominal setting
±3
mV
T
A
= –10°C to +60°C, nominal setting
–15
15
mV
T
A
= –40°C to +85°C, nominal setting
±5
mV
T
A
= –40°C to +85°C, nominal setting
–25
25
mV
V
(OVP_DLY)
Overvoltage detection delay
Nominal setting (3.3 ms steps)
10 ms to
6753 ms
in 3.3 ms
steps
ms
V
(UVP)
Undervoltage detection range
Nominal setting (50.6 mV steps)
1.012 V
to 4.048
V in 50.6
mV steps
V
SLUSE14B – DECEMBER 2020 – REVISED DECEMBER 2021
Copyright © 2021 Texas Instruments Incorporated
19
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