Tektronix 3B5, Инструкция по эксплуатации

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Circuit Description —Type 3B5
SW940B
XI
X10
X100
XI
X100
Magnifier Logic to
Delay and Timing
Circuit and Readout
Logic Circuit
Bar Magnifier Logic
to Sweep Generator
and Delay and Tim­
ing Circuit
Fig. 3-32. Delayed Sweep Magnif er Control circuit logic block diagram.
lector current flows through B925 and the EXT light comes
on. This bulb drops about six volts of the — 12-volt level
at the collector of Q925 to provide current to the — 6-volt
output line. The collector level of Q925 provides the External
Power output. In addition, the collector level of Q925 is
connected to Q905 through D902 and to Q915 through D912
to lock out the Seek and Manual Mode Control circuits.
Since Q915 is held off, K915-1 connects — 12.2 volts to the
Seek/External Power output.
Interconnecting Diagram
General
Diagram 9 shows the interconnections between Intercon­
necting Plug P21, PROGRAM connector J30, Logic Card
connector J400 and Counter Card connector J700. Although
these interconnections are shown in part on other diagrams,
this diagram gives an overall view of the interconnections.
This diagram also includes the Delayed Sweep Magnifier
Control circuit which is described below.
Delayed Sweep
Magnifier
Control
Fig. 3-32 shows a block diagram of the Delayed Sweep
Magnifier Control circuit. This circuit is controlled by Q944
and the DLY'D SWP MAG switch in Seek and Manual Mode
operation. For External Mode operation, the bias level is
disconnected from Q944 and the circuit is controlled by
external program magnifier logic through terminal 33, 34
or 36
of J30.
However, circuit operation is
the same
regard ­
less of the mode of operation. Table 3-1 lists the typical
logic output levels on the magnifier logic lines.
For XI magnification, the anodes of D947 and D949
are held at zero volts by Q944 or the external program X 1
magnifier logic at terminal 33 of J30. This holds the XI
(bar XI magnifier) logic line at zero volts along with the
X10 and XI 00 logic lines through D947 and D949. The
XI magnifier logic level drops to about — 7 volts where
it is clamped by D 348 and D349 in the Delay and Timing
Circuit. The XI 00 (bar XI 00 magnifier) logic level is also
set at about — 7 volts through D944.
For X10 delayed sweep magnification, the anodes of
D946 and D948 are held at zero volts by the input level
which also holds the X 1 and XI 00 magnifier logic lines
at zero through D946 and D948. The X10 magnifier logic
line is p ulled to — 12 volts through resistor R949 and both
the Xl and XI 00 magnifier logic lines are held at about
— 12 volts through D945 and D947.
X 100 delayed sweep magnification places zero volts on
the X 1 00 magnifier logic line. The X 1 and XI 00 magni­
fier logic lines are held at zero volt s thr ough D944 and D945.
D947 is reverse biased and the X 1 magnifier logic line
drops to about —12 volts through R204 (Sweep Generator
circuit). D949 is reverse biased and the XI 00 magnifier
logic line rests at about — 5.5 volts as established by the
3-45