Tektronix 3B5, Инструкция по эксплуатации

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Circuit Description — Type 3B5
turned on. This allows any portion of the sweep to be
magnified by selecting, with the DELAY control, the voltage
level on the sawtooth where the delayed sweep magnifier
is turned on. The DELAY control is calibrated in terms of
divisions of display. For example if the DELAY dial is set
to 5.00, the delayed sweep magnifier magnifies the portion
of the sweep beginning five divisions after the start of the
sweep.
For X 1 operation, — 7 volt X1 magnifier logic is con­
nected to the base of Q346 through D348. The base of
Q346 goes negative and is clamped at about — 6 volts by
D349. Q346 is reverse biased and the Delay Comparator
stage is locked out so the sweep can not be magnified
(note the exception for the 0.1 μ s and faster decades). For
X10 and XI 00 delayed sweep magnification, the X 1
magnifier logic rises to zero volts to reverse bias D348 and
allow the Delay Comparator to switch at the level selected
by the DELAY control. This action is as follows: quiescently
at the start of the sweep, about two milliamps of current is
flowing through R349. Current is also flowing through D338.
The current through D338 is a combination of the current
supplied by R337 and the current supplied by R336. The
current through R336 can be varied between zero and one
milliamp by changing the emitter level of Q333 with the
DELAY control, R331. R331 is a 10-turn potentiometer to
provide precise control of the current through R336. R330
and R333 provide adjustment for the voltage potential across
R331. This allows R331 to be accurately calibrated for delay
in terms of divisions of CRT display. When R331 is fully
counterclockwise (minimum delay), the emitter of Q333 is at
its most positive level and little or no current flows through
R336. Therefore, there is no additional current at the base
of Q346 which must be overcome to switch the comparator.
However, in the fully clockwise position (maximum delay)
about one milliamp of current flows through R336. This, in
effect, adds an additional milliamp of current at the base
of Q346 which must be overcome before the comparator
can switch.
Quiescently, Q356 is on and controls the conduction of
the comparator. The base of Q356 is held at about — 3
volts as established by divider R352-R353 from — 100 volts
to ground. Therefore, the base of Q346 must rise more
positive than about — 3 volts before it can come on. When
Q356 is on, the delayed sweep magnifier circuits are locked
out. When Q346 turns on, the delayed sweep magnifier
circuits are turned on also.
In addition to the quiescent currents flowing through R336,
R337 and R349, the sawtooth voltage is connected to the
base of Q346 through R309 and C309. This produces a
current change between about zero and one milliamp at the
base of Q346 as the sawtooth voltage rises. For minimum
delay (zero current through R336) the two milliamp current
flow through R349 and R337 holds the base level
of
Q346
very near its switching level. Then as the sawtooth starts
to run up, only a slight level change at the base of Q346
turns it on. The delayed sweep magnifier circuits are turned
on at the start of the sweep to magnify the total display.
For maximum delay (maximum current through R336) the
additional current from Q333 allows the base level of Q346
to go more negative. D349 clamps the base of Q346 at
about — 6 volts. Now, when the sawtooth starts to run up,
it must offset this extra current supplied by Q333 before
Q346 can switch. This will be near the positive peak of the
sawtooth to turn on the delayed sweep magnifier circuits
at the tenth division of display. Only the portion of the
trace following the tenth division is magnified (the sweep
length is increased several divisions for magnified operation;
see the Sweep Generator discussion). Operation of the
Delay Comparator for delay between these two extremes is
much the same. A precise amount of current as determined by
the DELAY control is added to the circuit by Q333. This
determines the amount that the sawtooth must run up before
the Delay Comparator is switched, thereby determining the
point on the sweep where the magnifier is turned on.
In the External Mode of operation, —12.2 volts External
Power is applied to the anode of D338 through D337. D338
is reverse biased and the DELAY control and Q333 are dis­
connected from the Delay Comparator stage. Then, an
external program delay current can be supplied through
terminal 17 of J30. The stage operates in a similar manner
to that described for internal delay. However, since R336 and
R337 are disconnected, the external program delay control
sets the total quiescent current level in the circuit. Q343
provides 10 times current gain to provide more linear control
of the external program delay.
For the 0.1 μ s and 10 ns timing decades, the 0.1 μ s (h)
decade logic line is at — 12 volts. This level is connected
to the base of Q356 through D354 and R354 to hold Q356
reverse biased, and the magnifier circuit remains on to mag­
nify the total sweep for the 0.1 μ s timing decade. In the 10 ns
timing decade, 10X gain of the 0.1 μ s timing decade is
provided by the Horizontal Amplifier. The Delay Compara ­
tor stage has no affect upon the turn-on point of the mag ­
nified circuits in these timing decades so the total sweep
is magnified.
Timing Resistor
The multiplier logic applied to the Timing Resistor deter­
mines the sweep rate within the decade established by the
Timing Capacitor. Resistor R381-R382-R383 form the "1 ” tim ­
ing group, R384-R385-R386 form the “ 2" timing group and
R387-R388-R389 form the “ 5 ” timing group. To select a
timing group, either D317, D318 or D319 is allowed to
conduct by reverse biasing the corresponding logic diode
D391, D392 or D393 with the multiplier logic level. This
level is —12-volts for the multiplier logic line to the timing
group desired and zero volts for the other two logic lines.
The timing current through the two timing groups not selected
is shunted to the corresponding multiplier logic lines. For
example, to select the "2" timing group, — 12 volts is applied
to the “ 2 ” logic line and zero volts to the "1" and "5"
logic lines. The anode level of D317, D318 and D319 is at
about —3.5 volts. Therefore, the zero-volt multiplier logic
level applied to the "1" and "5" logic lines forward biases
D391 and D393 to shunt the "1" and “ 5" timing current. The
“ 2" logic reverse biases D392 and allows the "2" timing
current to pass to the Timing Capacitor through D318.
Further selection of the specific timing resistor within each
timing group provides X 1, X10 or X 1 00 sweep magnifi­
cation. This is explained under X10 and X 1 00 Magnifier
Gates.
In the 10 ns decade, — 12 volts 10 ns (i) decade logic is
connected to the timing circuit through R390 and D390.
This adds approximately 10% more current to the timing
circuit for the 10 ns timing decade to improve timing accu­
racy.
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