Tektronix 2230, Руководство по обслуживанию

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Theory of Operation— 2230 Service
One transistor in each side of the output differential
amplifier pairs of U310 has its base bias set to a fixed
level by the divider network formed by R321 and R322.
The bias voltage of the other transistor in each pair is con­
trolled by the CHI TRIG signal from the Trigger Switch cir­
cuitry. When the CHI TRIG signal is HI, the transistors in
each output pair with the collectors connected together
(pin 6 and pin 14) are biased on, and the other transistors
in the output pairs are off. The collector signal currents of
the conducting transistors are equal in amount but of
opposing polarity, so the signal is cance'ed. When the
CHI TRIG signal is LO, the other transistors in each pair
are biased on, and a differential signal is developed across
output load resistors R314 and R315 to cove the Internal
Trigger Amplifier.
In te rn a l T rig g e r A m p lifie r
The Internal Trigger .Amplifier converts the differential
trigger signals from the Vertical Preamplifiers into a
single-ended signal that drives the X-Axis Amplifier and the
A and B Trigger Level Comparators.
Differential signal current is applied to the emitters of
U350D and U350E. The collector current of U350D is
changed to a voltage signal and inverted by U350C. The
opposite-phase collector current of U350E produces a volt­
age drop across R359 which is in phase with and adds to
the voltage across R360 at the collector of U350C. The
summed voltages appear at the base of U350A. Feedback
resistor R357 provides thermal bias stabilization for
U350C.
Emitter-follower U350A buffers the signal and shifts the
dc level back to 0 V. The emitter output signal of U350A
drives the X-Axis Amplifier, the B Trigger Level Compara­
tor, and the base of emitter-follower U350B. The emitter
signal of U350B in turn supplies the A Internal Trigger sig­
nal. The circuit arrangement of U350A and U350B, with
the common collector current path through R363, pro­
duces thermal bias stabilization of the two transistors.
T rigger Sw itching Logic
Either Channel 1, Channel 2, or VERT MODE Internal
Trigger signals may be selected by A&B INT switch S555
when A SOURCE switch S392 is set to INT. The INT posi­
tion of the A SOURCE switch applies a voltage that
reverse biases both CR393 and CR399 to stop the exter­
nal trigger signal and the line trigger signal from reaching
the A Trigger Level Comparator. The A Internal Trigger
Signal from the emitter of U350B is passed to the A
Trigger Level Comparator through forward-biased diode
CR372.
CHANNEL 1. For triggering from Channel 1, the A&B
INT switch is set to CH 1. The XY line connected to S555
is at ground potential, holding pin 4 of U555B LO. The out­
put of U555B is then also LO, and the Channel 1 signal
has a path through U310. At the same time, the Channel 2
signal path through U335 is shut off by the outputs of
U555G and U565B both being HI.
CHANNEL 2. For triggering from Channel 2, the A&B
INT switch is set to CH 2, and U555C pin 10 and U555D
pin 12 are LO. The outputs of both AND-gates are then
forced LO. A LO output from U555C enables the Channel
2 signal path through U335, and the HI outputs from
U555B arid U565C disable the Channel 1 path through
U310.
VERT MODE. When the A&B INT switch is set to
VERT MODE, the trigger source is selected by the two
VERTICAL MODE switches. For all VERTICAL MODE
switch combinations except BOTH-CHOP, the base of
Q541 is HI. The inputs and outputs of U555B, U555C, and
U555D are then all HI, and trigger signal selection is done
by flip-flop U540A in the Channel Switch Logic circuit
(Diagram 2) using the CHI ON and CH2 ON control sig­
nals going to U565B and U565C.
With Channel 1 selected (VERTICAL MODE switch set
to CH 1), both inputs to NAND-gate U565C are HI. The
output of U565C is then LO, and U310 is biased on to
select Channel 1 as the Internal Trigger signal source. The
LO CH2 ON signal from the Q output of U540A is applied
to U5653, and the CH2 TRIG line at the output of U565B
is forced HI to shut off the Channel 2 Trigger signal path.
When Channel 2 is selected (VERTICAL MODE switch
set to CH 2), the outputs of U540A, U565B, and U565C
will be the reverse of the states described for Channel 1
selection, The Channel 2 signal is then selected as the
Internal Trigger signal source, and the Channel 1 Trigger
signal path through U310 is shut off.
With ALT VERTICAL MODE selected, the inputs of
NAND-gates U565B and U565C toggle (change state) with
each sweep. The outputs of the two gates also toggle,
and U31C1
and U335 are alternately biased on to select the
displayed channel signal as the Internal Trigger source.
In the ADD VERTICAL MODE position, both inputs to
U565B arid to U565C are HI, making the outputs of both
gates LO. Both the Channel 1 and the Channel 2 signal
path are turned on by biasing on U310 and U335 together.
The output currents of both Trigger Preamplifiers are
summed in the Internal Trigger Amplifier to produce the
Internal Trigger signal.
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