Tektronix 2230, Руководство по обслуживанию

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Theory of Operation— 2230 Service
in addition, when one of the Communication Options is
installed, the RDY1 input (U9104 pin 4) is used to syn­
chronize the operation of the Microprocessor with the
asynchronous activity of the GRIB (General Purpose Inter­
face Bus) or RS-232-C Options for parallel or serial data
transfer via the external communications port.
Resistor pack R9113 is a data bus pull-up. During nor­
mal operation, the resistor pack generates the interrupt
vector pointer. During the hardware kernel test, the resis­
tor pack generates the NOP instruction.
Latch and Buffer
Addressing is done using dedicated address bus lines.
Address latch U9112 demultiplexes the address bus
(separates the address and data bytes). When an address
is valid, the Microprocessor sets the address-latch enable
(ALE) HI (U9111 pin 25). Both U9112 and U9114 are
clocked to latch the address bits. The latched bits are held
until the Microprocessor places a new address on the
busses and again sets the ALE; signal HI. Some bits pass­
ing through U9114 have status information multiplexed
with the address, so U9114 also functions as a demulti­
plexer.
Decoder
In addition to providing specific addresses to internal
locations within memory devices, the addresses are
decoded to provide enabling signals for blocks of
addresses
and to control the selection of I/O
(Input/Output) devices. Table 3-1 shows the instrument’s
memory map.
In normal operation, address block decoder U9106 is
always enabled. One-half of the dual 1-of-4 decoder looks
at address bits A14 and A15. Latched address bits A18
and A19 from U9114 are looked at by the second half of
the device.
I/O address decoding is performed by U9105. To per­
form its decoding, it must be enabled by the decoded out­
put of U9106. The lower half of U9105 is controlled by a
logic gating circuit formed by U9101D, U9102A, and
U9102D. The lower half becomes enabled when either RD
or WR is Low and BLOCK-O and IO SEG are both LO.
The upper half of U9105 is enabled only when address bits
A12 and A13 are both HI, setting pin 9 of U9105 LO.
ROM
The operating system firmware is contained in two 64K
by 8-bit read-only memories (U9110 and U9109). Immedi­
ately after the power-up reset ends, the Microprocessor
automatically fetches the first command from the reset
vector (address 0FFFF0), and begins program execution.
Other interrupts: to the Microprocessor cause vectoring to
addresses that start the interrupt handling routines. The
NMI (non-maskable interrupt) vector is at 00008, and the
Maskable Interrupt (INTR) is vectored to 03FC (both inter­
rupt vectors are in RAM).
Store Panel Controls and Buffer
The open or closed position of the Storage Panel Con­
trols is passed to the Microprocessor via two octal bus
drivers, U9301 and U9302. Each bus driver transfers eight
individual data bits to the data bus when enabled. Enabling
of the bus drivers is done by address line A2, which goes
to both drivers, and decoded input/output enabling lines,
going separately to each driver. Both enabling inputs must
be LO on each 1C to pass the input data bit to the data
bus.
The Microprocessor communicates with the other
devices on the data bus via Octal Bus Transceiver U9113.
Two signals from the Microprocessor control enabling of
the Transceiver and direction of the data flow. When the
DEN_ signal is LO U9113 is enabled for transfers, and the
DT/R signal sets the direction of the transfer. IO/M
qualifies the transfer to allow pull-ups to assert an inter­
rupt number on the bus during interrupt cycles. While the
address and data are available on the bus side of this
transceiver, only the data time slot is used.
Non-Storage Front-Panel Controls
There are many front-panel controls that do two things
at the same time; control the real-time scope mode, and
tell the Microprocessor what is being selected or modified.
These controls include the vertical position controls, the
vertical gain controls, the A and B time per division con­
trols, the three major trigger mode controls, the vertical
coupling controls, the sweep mode control, and the delay­
time control. In addition, the probe-coding ring is read to
determine true Volts per Division. In addition to acting as
the user interface to the Microprocessor, the 1K/4K and
STORE/NON STORE switches select the reference volt­
age applied the A and B timing resistors in the Sweep
Generator circuitry.
STATUS ADC AND BUS INTERFACE
Front-panel control settings and the operating status
are passed to the Microprocessor via the Bus Interface.
Digital signals that can be read directly as data bits are
buffered onto the Data bus either via octal bus driver
U6102 or U6103. Analog voltages are converted to digital
data bytes by analog-to-digital converter U6105. The ana­
log signals are multiplexed to a buffer amplifier either by
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