Supero SUPERSERVER 5013G-6, Руководство пользователя

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S
UPER
S
ERVER 5013G-6/5013G-i Manual
1-2
1-2 Mainboard Features
At the heart of the SuperServer 5013G-6/5013G-i lies the P4SGR/P4SGE, a
single processor motherboard designed to provide maximum performance.
Below are the main features of the P4SGR/P4SGE. See Figure 1-1 for a
block diagram of the 845GE chipset.
Chipset Overview
Intel’s 845GE chipset is made up of two main components:
The Graphics Memory Controller Hub (GMCH)
The I/O Controller Hub (ICH4)
Graphics Memory Controller Hub (GMCH)
The GMCH includes the host (CPU) interface, memory interface, ICH4 inter-
face and 4xAGP interface for the 845GE chipset. It contains advanced
power management logic and supports a single channel of DDR SDRAM.
The AGP 2.0 interface supports 4x data transfers and operates at a peak
bandwidth of 1.6 GB/sec.
An external graphics accelerator card is not required due to the integrated
graphics in the 845GE chipset. (If the system BIOS detects an external
AGP device, it will disable the integrated graphics.) The integrated graphics
c o n t r o l l e r d e l i v e r s 3 D , 2 D a n d v i d e o c a p a b i l i t i e s , i n c l u d i n g v i d e o
conferencing applications. The controller does not utlilize local memory, but
accesses graphics data located in system memory at speeds of up to 2.1
GB/s (DDR-266). It also includes a cache controller to avoid frequent
memory fetches of recently accessed texture data.
I/O Controller Hub (ICH4)
The ICH4 is a fourth-generation I/O Controller Hub subsystem that integrates
many of the input/output functions of the 845GE chipset, including a two-
channel ATA100 Bus Master IDE controller. The ICH4 also interfaces with
the PCI cards, the AC'97 Audio CODEC and the various communications
ports. Nearly all communications between the GMCH and the ICH4 takes
place over the hub Interface, which is a 66 MHz/266 MB/s bus.