Sun Microsystems Ultra 5, Руководство по обслуживанию

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Appendix C Functional Description C-27
C.2 Clocking
There are five system clock domains: CPU, second level cache SRAMs, UPA, PCI,
and miscellaneous clocks for the various IO devices.
C.2.1 CPU and UPA Clocking
The CPU and UPA clocks are generated using a frequency synthesizer on the CPU
module. The synthesizer output frequency is divided by four, before being driven to
the CPU and SRAMs. In addition, one synthesizer output frequency is divided by six
and is gated to the CPU module and to the UPA graphics slot as the UPA clock.
C.2.2 PCI Clock Generation
All PCI clocks are generated on the motherboard. Additionally, two 66-MHz PCI
clocks are gated to the CPU module through the module connector.
TABLE C-9
lists
the generated PCI clocks.
The motherboard supports two different PCI clock generators; the ICW48C60-422G
clock generator or the CY2254A-2 clock generator.
TABLE C-10
and
TABLE C-11
list the
PCI clock generator frequency select bits for the ICW48C60-422G and the
CY2254A-2 PCI clock generators, respectively.
TABLE C-9
PCI Clocks
Component 66 MHz 33 MHz
CPU module 2
APB 1 1
PCI expansion slots 2
RISC 1
PCIO 1