Sun Microsystems Ultra 5, Руководство по обслуживанию

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C-20 Sun Ultra 5 Service Manual • February 2000
C.1.5.2 PCIO
The PCI-to-EBus/Ethernet controller (PCIO) ASIC interfaces to the PCI bus and
implements three major functions:
■
10-/100-Mbit Ethernet media access controller (MAC)
■
Asynchronous 8-bit EBus2 interface
■
Four dedicated DMA channels:
■
Parallel port
■
Audio capture/record
■
Audio playback
■
Diskette
A PCIO ASIC interrupt router directs the channel engine interrupts to the
appropriate device. EBus2 interrupts (only those associated with a DMA channel)
are assigned to
INTA#
and Ethernet interrupts are assigned to
INTB#
. In PC card
mode, this is in add-in mode. The PCIO ASIC has separate interrupt lines for each
internal device.
INTA#
becomes
ent_irq_1
,
INTB#
is unused,
INTC#
becomes
pport_irq_1,
and
INTD#
becomes
fpy_irq_1
. Interrupts from the audio capture
are routed to
audio_cap_irq_1
while interrupts from audio playback are routed to
audio_pb_irq_1
.
In the motherboard mode, interrupts from external EBus2 devices not associated
with DMA channels (for example, keyboard and mouse) are connected directly to
the system interrupt controller (RISC) ASIC.
C.1.5.3 RISC
The reset, interrupt, scan, and clock (RISC) ASIC combine the five reset conditions
into three signals to the CPU module. Based on these signals, the CPU module sets
the proper control register bit to enable the software to identify the source of the
reset. The following figure shows the system reset functional block diagram. The five
reset conditions include:
■
POWER_GOOD
from power supply
■
Scan
control
■
Button
POR
■
Button
XIR
■
Scan
XIR