Sun Microsystems Ultra 5, Руководство по обслуживанию

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Appendix C Functional Description C-3
C.1.1 CPU Module
The system CPU module is the UltraSPARC-IIi processor. The CPU module is a high-
performance, highly-integrated superscalar processor implementing the SPARC-V9
64-bit RISC architecture. The CPU module is capable of sustaining the execution of
up to four instructions per cycle, even in the presence of conditional branches and
cache misses. This sustained performance is supported by a decoupled prefetch and
dispatch unit with instruction buffer. The CPU module supports both 2D and 3D
graphics, as well as image processing, video compression and decompression, and
video effects via the sophisticated visual instruction set (VIS). VIS provides high
levels of multimedia performance, including real-time video compression/
decompression and two streams of MPEG-2 decompression at full broadcast quality
with no additional hardware support. The CPU module characteristics and
associated features include:
■
SPARC-V9 architecture compliant
■
Binary compatible with all SPARC application code
■
Snooping or directory-based protocol support
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Four-way superscalar design with nine execution units
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Four integer execution units
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Three floating-point execution units
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Two graphics execution units
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Selectable little-endian or big-endian byte ordering
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64-bit address pointers
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16-Kbyte non-blocking data cache
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16-Kbyte instruction cache with single cycle branch following
■
Power management
■
Software prefetch instruction support
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Multiple outstanding requests
The Ultra 5 system may contain a 270-MHz, 333-MHz, 360-MHz, or 440-MHz CPU
module. The following table identifies the cache and SRAM for each module.
TABLE C-1
Ultra 5 CPU Module Cache and SRAM
Module Second-Level Cache Data SRAMs TAG SRAMs
270-Mhz 256-KByte 2 - 32K x 36 1 - 32K x 36k
333-Mhz 2-Mbyte 4 - 256K x 18 1 - 64K x 18
360-Mhz 256-Kbyte 2 - 32K x 36 1 - 64K x 18
360-Mhz 2-Mbyte 4 - 256K x 18 1 - 64K x 18
440-MHz 2-Mbyte 2 - 256K x 36 1 - 256K x 18