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5 - Peripherals
05-int
5.2.3 Global interrupt enable bit
RESET and TRAP (explained in the next paragraph) are non-miscible interrupt; the other
sources of interrupt may be inhibited as a whole thanks to the I bit of the condition code reg-
An interrupt is requested
Its relative pending bit is set
Is the I bit of the
CC register reset ?
this interrupt will
be serviced when
the I bit is reset
The core finishes its current instruction.
PC, X, A, CC are pushed onto the stack.
The I bit is set.
The PC is loaded with the address of the interrupt vector.
The interrupt program starts.
At the beginning of this program, you can
temporarily save data if needed, such as the Y register.
You must restore them at the end.
Before returning, the pending bit must be cleared.
The iret instruction causes:
- CC, A, X, PC to be popped from stack.
- The interrupted program to resume or another interrupt
program to start.
Yes
No
The interrupt mechanism of the ST7 family
Содержание ST7 Series
Страница 1: ...ST7 8 BIT MCU FAMILY USER GUIDE JANUARY 1999 1 ...
Страница 238: ...238 317 8 C Language and the C Compiler 08 Burn bmp Then use the EPROMer programmer software as described in Chapter 7 ...
Страница 289: ...289 317 10 Second Application a Sailing Computer 10 befor Bs Rw Vw VMG AlphaR AlphaV Before the wind ...