ST ST7 Series, Руководство пользователя

Страница: 279 / 317

279/317
9 - A Carrier-current System for domestIc Remote Control
TempKeyCode |= 0x10 ; /* Set least-significant bit to one */
At the end of the reception, these codes can be checked to determine if the receiver has any-
thing to do with them. In the checking phases, if the bit is found to be incorrect, the receive
process is aborted by setting
CycleNumber
back to 1:
if ( ( ( TempKeyCode & 0x10 ) != 0 ) == CarrierDetected )
CycleNumber = 1 ; /* Reset the whole process if incorrect check bit.
As the X-10 standard states, each command is sent twice. The receiver is also designed so
that two successive frames are received in succession. After the second frame is received, the
codes received in the first frame are compared with the codes received in the second frame.
If they match, the codes are considered valid and are passed to the main program to produce
the expected effect.
9.3.3.2 Main program
The main program starts with a few initialization functions that are very similar to that of the
transmitter. It then runs into an endless loop that controls the sequencing of the blind motion.
Timer B control
Timer B is used to generate an interrupt after a predefined delay, using the Compare 1 reg-
ister. When a delay is required, the
WaitDelay
function is called. This function sets up Timer
B by first setting the free-running counter to FFFC, then setting the Compare 1 register to the
required time delay (-5 to compensate from the resetting to FFFC). Then, all interrupt requests
are cleared, and the interrupt on compare is unmasked.
This function is partly written in assembler, to avoid the side-effects of the compiler regarding
the order of the assignments. While waiting, the core is set to the Wait state using the
WFI
in-
struction. This reduces the power consumption. Since there are other interrupts, exiting from
the wait state does not necessarily mean that the time has elapsed. To check whether the time
has elapsed, the
WFI
instruction is executed repeatedly in a loop that is only exited when the
condition is fulfilled. This condition,
TimeElapsed
, is actually a macro defined as follows:
#define TimeElapsed ( TBSR & ( 1 << OCF1 ) )
This expression is only true if the OCF1 bit in the TBSR register is set.
The Output Compare Interrupt Enable bit enables both Compare 1 and Compare 2 events at
the same time. Here, it is necessary to clear the OCF2 Compare 2 event flag before enabling