ST ST7 Series, Руководство пользователя

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5 - Peripherals
5.5.2 Free running counter
The main component of the 16-bit timer is the Free-Running counter, called the CHR (Most
Significant Byte) and CLR (Least Significant Byte) register. This is a binary counter that incre-
ments by one at each clock cycle, hence its name. It is possible to read the value of this timer,
but it is only possible to reset it to its start value that is FFFCh, either under program control or
automatically depending on the working mode selected.
Each time the free-running counter overflows from FFFFh to 0000, the TOF bit (Timer Over-
Flow) is set in the TSR status register. Resetting this bit involves reading the CLR register. In
cases where it is necessary to read the free-running counter but it is not desirable to clear the
TOF bit, the same free-running counter is accessible at another register address called ACLR
where reading does not alter the TOF bit.
5.5.2.1 Reading the free running counter
The free running counter can be read at any time. However, since this is a 16-bit register, and
the core is an 8-bit one, it is not possible to take a snapshot of the counter value at once. This
can lead to data desynchronization problems, as mentioned earlier in this book.
To avoid this problem, the timer has a buffering feature that works as follows:
When the high byte of the counter is read, the value of the low byte is captured in a transparent
latch. When the program reads at the address of the low byte of the counter, it actually reads
the value previously frozen in the latch, and the latch is re-enabled. This means that when the
low byte of the counter is read, for fast clock rates, the counter may not have the value read.
The program must take this into account.
05-read
Reading the free running counter
The low byte of the counter
can be read "on the fly"
When the high byte of the counter
is read, the low byte is bufferised
until a reading access to it is performed