ST ST7 Series, Руководство пользователя

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9 - A Carrier-current System for domestIc Remote Control
As described in the ST72251 data sheet, a mechanism to avoid data desynchronization pre-
vents any captures occuring once the high register has been read, until the low register has
been also read. This implies that we must ensure that the high byte is read first, then the low
byte. Due to the compiler optimization, the only way to guarantee the right order is to use the
assembler. This is why the capture register is read using the code above. The convention of
the compiler is that in a 16-bit variable, the most significant byte comes first in the address
space, thus the notation
Position:1
for the low-order byte.
The phase deviation is then computed as the difference between the capture register value
and the position of the rising edge of the pulse. This deviation is divided by 16 by shifting it
right four times (here the time for a normal division would have been too long) to reduce the
loop gain, and the deviation is clamped to less than 0.5% of the nominal frequency. The final
value for the period is obtained by adding this signed value to the nominal period value. This
value is stored in the global variable
TimerAPeriod
that is used at the beginning of the inter-
rupt service routine to update the compare register. This ensures that the compare register is
updated separately from the comparison, avoiding the problem that would occur if the compar-
ison occured between the writes of the two bytes of the register, as the value of the period is
computed on zero-crossing interrupts, that has no particular relationship with the compare
events, especially when the system is seeking synchronization.
The nominal period is defined in the
X10XMIT.H
header file, as follows:
/* #define F60HZ */ /* Remove the comments for 60 Hz. */
#ifdef F60HZ
#define TIMER_A_PERIOD 5555 - 5 /* Nominal for 60 Hz, in 1/2 microseconds
*/
#else
#define TIMER_A_PERIOD 6666 - 5 /* Nominal for 50 Hz, in 1/2 microseconds
*/
#endif
This source text is set for a 50 Hz power system. To change it for a 60 Hz system, the first
#define
should be re-instated by removing the comment marks (/* */). For 50 Hz, the timer pe-
riod must be 1/6 the line period, that is, 3.333 ms. Since the timer is driven by a 2 MHz clock,
this makes 6666 ticks. But when the Compare 2 event occurs, the counter is reset to FFFCh,
that is -5 in two's complement notation. Thus the nominal value for the Compare 2 register is
actually 6666 - 5, or 6661.