RadioProcessor
System Architecture
Figure 1, below, presents the architecture of the RadioProcessor. The RadioProcessor consists of three
major components: the data acquisition core, the excitation core, and the PulseBlaster timing engine which
provides high-resolution timing control for the entire system.
The acquisition core captures an incoming RF signal using a high-speed, high resolution Analog to Digital
converter (ADC). This signal is then demodulated digitally using quadrature detection and filtered to reduce
the signal to baseband. The detection and filtering system is highly configurable and can easily be customized
by the user for a wide variety of applications. The baseband signal can then be averaged with previous data
acquisition scans and is stored in an internal RAM. This data is then available to be retrieved onto the host
computer at the user's convenience.
The excitation core can produce both RF Analog signals as well as digital outputs. The RF output is
generated using an internal Direct Digital Synthesis (DDS) core, and can generate frequencies from DC up to
half the DDS clock. The generated signal is converted to the Analog output by an on board digital-to-analog
converter (DAC). This DDS core also drives the detection of the acquisition core, so signal coherence is
maintained between acquisition and excitation cores. High resolution programmable digital outputs are also
available for use in controlling external hardware.
At the heart of the system is the PulseBlaster pulse/pattern generator timing core, which uses a robust
instruction set designed to allow the creation of complex pulse sequences with ease. This timing core controls
all aspects of the systems functionality, such as triggering data acquisition, controlling the frequency and
gating RF output, etc. The digital outputs are also controlled with this core. Six digital outputs are available by
default, and more are possible if some features of the excitation and acquisition cores are not used. The
PulseBlaster core utilizes an 80-bit Very Long Instruction Word (VLIW) which enables dynamic timing delays
for each instruction. For more information about the PulseBlaster core, please see the
2020-10-07
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Figure 1:
RadioProcessor Architecture. The master clock oscillator signal is derived from an on-chip PLL
circuit typically using a 50 MHz on-board reference clock.
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