Pin
No.
Symbol
Signal
name
In/Out
Function
34
NC
NC
—
NC
35
CS1
S A1
In
Channelselect signal
36
CLK/TRG3
S TM1
In
External clock / timer signal
37
CLK/TRG2
S TM0
In
External clock / timer signal
38
NC
NC
—
NC
39
NC
NC
—
NC
40
CLK/TRG1
S INTS
In
External clock / timer signal
41
CLK/TRG0
VCC
In
+5V
42
NC
NC
—
NC
43
+5V
VCC
—
+5V
44
NC
NC
—
NC
2-6.
µ
PD71037
DMA CONTROLLER
The
µ
PD71037 is a direct memory access controller (DMAC) for the
micro processor system. It provides higher processing speed and
lower power consumption in comparison with those in conventional
use. Each of the four built-in DMA channels has 64-KB addresses
and the function of counting the number of bytes of transferred data,
and can transfer data from I/O to memory and from memory to
memory as well.
1) FEATURES
•
The clock speed is 10 MHz, twice that of the
µ
PD8237A-5 (clock
speed of 5 MHz).
•
Each of the four DMA channels can be operated independently.
•
Each channel can be self-initialized.
•
Data is transferrable from memory to memory.
•
Data in memory can independently initialized by block.
•
High speed data transfer:
3.2 MB/sec. (clock seed of 10 MHz, normal transfer mode)
5.0 MB/sec. (clock speed of 10 MHz, compression transfer mode)
•
The number of DMA channels can directly be expanded
(Expansion mode).
•
END input when data transfer is finished.
•
Software DMA request available.
•
CMOS
•
Low power consumption
2) Pin configuration
3) Pin configuration
Pin
No.
Symbol
Signal
name
In/Out
Function
1
READY
READY
In
Ready signal
2
HLDAK
HLDAK
In
Hold acknowledge signal
3
ASTB
S ASTB
Out
Address strobe signal
4
AEN
S AEN
Out
Address enable signal
5
HLDRQ
HLDRQ
Out
Hold request signal
6
NC
NC
—
NC
7
CS
CS
In
Chip select signal
8
CLK
CLK
In
Clock
9
RESET
SRNRESET
In
Reset signal
10
DMAAK2
S DACK2
Out
DMA acknowlidge signal
11
DMAAK3
S DACK3
Out
DMA acknowlidge signal
12 DMARQ3
S DRQ3
In
DMA request signal
13 DMARQ2
S DRQ2
In
DMA request signal
14 DMARQ1
S DRQ1
In
DMA request signal
15 DMARQ0
S DRQ0
In
DMA request signal
16
GND
GND
—
GND
17
NC
NC
—
NC
18
A15/D7
S D7
In/Out Data bus
19
A14/D6
S D6
In/Out Data bus
20
A13/D5
S D5
In/Out Data bus
21
DMAAK1
S DACK1
Out
DMA acknowlidge signal
22
DMAAK0
S DACK0
Out
DMA acknowlidge signal
23
A12/D4
S D4
In/Out Data bus
24
A11/D3
S D3
In/Out Data bus
25
A10/D2
S D2
In/Out Data bus
26
A9/D1
S D1
In/Out Data bus
27
A8/D0
S D0
In/Out Data bus
28
NC
NC
—
NC
29
VDD
VCC
—
+5V
30
A0
S A0
In
Address bus
31
A1
S A1
In
Address bus
32
A2
S A2
In
Address bus
33
A3
S A3
In
Address bus
34
NC
NC
—
NC
35 END / TC
TC
In/Out End / Terminal cut signal
36
A4
S A4
In
Address bus
37
A5
S A5
In
Address bus
38
A6
S A6
In
Address bus
39
A7
S A7
In
Address bus
40
IORD
S IOR
In/Out I/O read signal
41
IOWR
S IOW
In/Out I/O write signal
42
MRD
S MRD
Out
Memory read signal
43
MWR
NC
—
NC
44
NC
NC
—
NC
READY
1
HLDAK
2
ASTB
3
AEN
4
HLDRQ
5
NC
6
CS
7
CLK
8
RESET
9
DMAAK2
1 0
DMAAK3
1 1
A3
33
A2
32
A1
31
A0
30
VDD
29
NC
28
A8/D0
27
A9/D1
26
A10/D2
25
A11/D3
24
A12/D4
23
µPD71037GB-3B4
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