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2-7. MB62H149

1) Outline

The MB62H149 is a semi-custom LSI chip for the peripheral circuits
in the SRN (SHARP Retail Network), its main function is to communi-
cate data with the host CPU and control the peripheral circuits and
transmission control circuits of the Sub CPU (Z-80). Fig. 2. shows the
general configuration of the functions:

Fig. 2

2) Internal functions

(1) Data handshaking circuit

Is used because data processing speeds vary and the timing of the
HOST CPU and SUB CPU do not synchronize, the MB62H149 is
used for data handshaking. When the data handshaking portion is
broken down, the system consists of a Write Signal from the HOST
CPU to the MB62H149, Read Signal from the MB62H149 of the SUB
CPU, Write Signal from the SUB CPU to the MB62H149 and Read
Signal from the MB62H149 of the HOST CPU, all of which from two
blocks as shown.

Fig. 3

Fig. 4

(2) Peripheral circuit

The peripheral circuit consists of an I/O address generation unit on
the SUB CPU, block dividing circuit, and the wait signal control unit.

Fig. 5

(a)

I/O address generation circuit

A total of 11 I/O addresses are generated by A0, A1, A4, A5 and
RD and WR signals.

(b)

CPU and DMAC wait signal control unit

Clocks into the CPU (Z-80), SUB CPU and its peripheral LSI,
DMAC and CTC are operated respectively on 4 MHz.
While, the ADLC (MC68B54) (Advanced Data Link Control) is
operated by the E (Enable clock) of 2 MHz according to restric-
tions in terms of the hardware of the LSI.
It is necessary to synchronize the timing of the write and read in
the ADLC.
To control synchronization, timing, and input, the wait signal
goes into the CPU for CPU access and into the DMAC for DMA
access. This block is a circuit to generate such wait signal.

(c)

Clock dividing circuit

This block divides the blocks according to the CLK supplied from
outside to generate the clock for CPU, DMAC and CTC and the
E and transmission clock rate (480 KBPS or 1 MBPS selectable)
for the ADLC.

(3) Transmission control circuit

The transmission control circuit is divided into the modem unit, carrier
detect unit, collision detect unit.

Fig. 6

(a)

Modem circuit

The transmission data input from the ADLC are PE modulated
(phase encoding modulation), the circuit to be output to the
transmission driver and the reception data input from the trans-
mission receiver are demodulated and produced at the ADLC.

(b)

Collision detect circuit

The data transmitted from the home station is received and
detects a collision on the transmission line by means of an
exclusive OR gate.

(c)

Carrier detect circuit

This circuit detects whether data is flowing on the transmission
line. It consists of a circuit which immediately senses a no data
status on the line. When data is not on the line the circuit func-
tions to sense an elapse of the fixed time rate. The immediate
sensing circuit is used for response testing and the delayed
sensing circuit is used for data testing.
The fixed time rate is selectable according to the transmission
speed as shown below via SRV-mode programming. Job #922.

Transmission speed

Delay time

1 MBPS

1.6m sec, 3.2m sec, 4.8m sec, 6.4m sec.

480 KBPS

3.2m sec, 6.4m sec, 9.6m sec, 12.8m sec.

MB62H149

Line

TRANS-
MISSION
CONTROL
CIRCUIT

PERIPHERAL
CIRCUIT

DATA HAND
SHAKING
CIRCUIT

TIMER
COUNTER