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15-1 CPU interface and modulator/demodulator
Here is its block diagram.
Fig. 20
16. SRN
The SRN of the UP-3300 is compatible with the ER-A750.
17. RS232
Two standard RS232 channels are compatible with the ER-A5RS.
However, while the ER-A5RS uses the IRQ2 terminal of the CPU for
interruption of the RS232, the UP-3300 cannot use the IRQ1 terminal
instead of it. (The IRQ2 terminal is used for IR as the SCK1 terminal.)
The standard RS232 is fixed to the logic channels 1 and 2. To the
built-in printer, logic channel 7 is assigned. Use the channels 3, 4, 5
and 6 for the ER-A7RS.
18. MCR
This paragraph describes MCR option (UP-E12MR2) control defined
by UP-3300 hardware architecture.
2 channels of the serial port (interchangeable with 8251) built in the
MPCA8 are used. 2 tracks of data are read simultaneously. Supports
the first and second tracks MCR of ISO. (UP-E12MR2)
18-1. CPU interface
The CPU interface for the USART (8251) and magnet card reader
(MCM-21) in the UP-3300 system is shown below.
Signal description
RCP1
TRACK 1 CLOCK PULSE
RDD1
TRACK 1 DATA SIGNAL
RCP2
TRACK 2 CLOCK PULSE
RDD2
TRACK 2 DATA SIGNAL
CLS1
TRACK 1 CARD DETECTION SIGNAL
CLS2
TRACK 2 CARD DETECTION SIGNAL
RCVRDY1
TRACK 1 DATA RECEIVING SIGNAL
RCVRDY2
TRACK 2 DATA RECEIVING SIGNAL
INTMCR
INTERRUPT SIGNAL OR-SYNTHESIZED from
RCVRDY and SYNC input
2 chip select signals for 8251 are generated inside MPCA8. The 8251
write recovery time is as follows:
18-2. MCR interface
The operating timing of the MCR interface signals is given below.
(1) Example of timing
(2) Detailed timing (relation between DATA and CLOCK PULSE)
The "NULL" CODE is basically written prior to the opening code. The
opening code detection algorithm is considered because data may
become corrupt before and after the CARD detection signal due to a
worn magnet stripe.
19. Touch panel interface
The 8251 built in the MPCA8 is used as serial communication with
the touch panel controller.
8251 (TPZ):
Located in 00FFB8h
∼
00FFBBh.
Interrupt:
Signal sending interrupt is connected to the INT3.
Signal receiving interrupt is connected to the INT2.
1
Duplex type: Full-duplex
2
Data rate: 9600 Bps
3
Synchronizing mode: Asynchronous
4
Signal level: TTL
5
Data format: 1 Start-bit
8 Data-bit
Stop-bit
Non parity-bit
20. 1-HOLE CLERK
On the UP-3300, 1-hole clerk key with up to 8 bits can be used.
The 1-hole clerk switch is controlled through the CKDC9 on the main
board.
UATX
UARX
UASCK
491KHz
TXD1
RXD1
SCK1
7.3728MHz
IRTX
IRRX
ASKRX
CPU
MPCA8
IR unit
IRDA modulation/
demodulation
ASK modulation/
demodulation
Divider
Baud rate X16
Baud rate
X
RPM851
CPU
ICI
INTMCR
RCVRDY1
RCVCLK2
RDD1
RCP2
RDD2
CLS1
RCVDT1
RCP1
/DSR1
CLS2
RCVDT2
8251 x 2
Integrated as MPCA8
in the UP-3300 system.
RCVCLK1
/DSR2
RCVRDY2
CLS1,
CLS2
RCVRDY1
RCVRDY2
INTMCR
SYNC
MPCA7
RDD1/RDD2
RCP1/RCP2
CLS1/CLS2
"0"
"1"
"1"
Approx. 16µs
Min. 16µs
RDD1/RDD2
RCP1/RCP2
TXD
DTR
RTS
RXD
CTS
DSR
TXC
RXC
TXRDY
TXEMPTY
SYNDET
D0~D7
C/D
RD
WR
CS
RESET
CLK
RXRDY
OPEN
OPEN
GND
GND
INT3
OPEN
OPEN
TPCKI
TPTXD
TPRXD
D0~D7
A0
RD
HWR
TP7(00FFB8h~00FFBBh)
RESET
PHAI(9.83)
INT2
8251 (USART)
9.83MHz 64
(153.59KHz)
÷
CKDC9
ST0 ST3
LS138
X2
/S2 /S9
/CFSR
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