3) Pin configuration
Pin
No.
Symbol
Signal
name
In/
Out
Function
1
XIN
XIN
In
25.175MHz
2
GND
GND
In
GND
3
AEN
GND
In
GND
4
/SBEH
/SBEH
In
System byte high enable
5
/IOWR
/IOWR
In
I/O write
6
/IORD
/IORD
In
I/O read
7
/SMEMW
/SMEMW
In
Meory write
8
/SMEMR
/SMEMR
In
Memory read
9
A21
GND
In
GND
10
A20
GND
In
GND
11
SA19
VCC
In
+5V
12
SA18
GND
In
GND
13
SA17
VCC
In
+5V
14
SA16
A16
In
Address bus
15
SA15
A15
In
Address bus
16
SA14
A14
In
Address bus
17
SA13
A13
In
Address bus
18
SA12
A12
In
Address bus
19
SA11
A11
In
Address bus
20
SA10
A10
In
Address bus
21
SA9
A9
In
Address bus
22
SA8
A8
In
Address bus
23
SA7
A7
In
Address bus
24
SA6
A6
In
Address bus
25
SA5
A5
In
Address bus
26
SA4
A4
In
Address bus
27
SA3
A3
In
Address bus
28
SA2
A2
In
Address bus
29
SA1
A1
In
Address bus
30
SA0
A0
In
Address bus
31
/BIOSEN
NC
In
NC
32
/REFRESH
/RFSH
In
Refresh signal
33
GND
GND
In
GND
34
VDD
VCC
In
+5V
35
SD15
D7
I/O
Data bus
36
SD14
D6
I/O
Data bus
37
SD13
D5
I/O
Data bus
38
SD12
D4
I/O
Data bus
39
GND
GND
In
GND
40
SD11
D3
I/O
Data bus
41
SD10
D2
I/O
Data bus
42
SD9
D1
I/O
Data bus
43
VDD
VCC
In
+5V
44
SD8
D0
I/O
Data bus
45
SD7
D15
I/O
Data bus
46
SD6
D14
I/O
Data bus
47
GND
GND
In
GND
48
SD5
D13
I/O
Data bus
49
SD4
D12
I/O
Data bus
50
SD3
D11
I/O
Data bus
51
SD2
D10
I/O
Data bus
52
SD1
D9
I/O
Data bus
53
SD0
D8
I/O
Data bus
54
GND
GND
In
GND
55
VDD
VCC
In
+5V
56
IOCHRDY
/VWAITI
Out
Channel ready signal
57 /MEMCS16
NC
In
NC
58
/IOCS16
NC
In
NC
59
GND
GND
In
GND
Pin
No.
Symbol
Signal
name
In/
Out
Function
60
VDD
VCC
In
+5V
61
DCLK
XCK
Out
Data shift clock
62
DISP
DISP
Out
Display enable
63
LP
LP
Out
Line pulse
64
FP
YD
OUt Frame pulse
65
UD7
DU7
Out
Upper data
66
UD6
DU6
Out
Upper data
67
UD5
DU5
Out
Upper data
68
UD4
DU4
Out
Upper data
69
UD3
DU3
Out
Upper data
70
UD2
DU2
Out
Upper data
71
UD1
DU1
Out
Upper data
72
UD0
DU0
Out
Upper data
73
GND
GND
In
GND
74
VDD
VCC
In
+5V
75
LD7
DL7
Out
Lower data
76
LD6
DL6
Out
Lower data
77
LD5
DL5
Out
Lower data
78
LD4
DL4
Out
Lower data
79
LD3
DL3
Out
Lower data
80
LD2
DL2
Out
Lower data
81
LD1
DL1
Out
Lower data
82
LD0
DL0
Out
Lower data
83
BACKON
BKLT
Out
Back light On
84
LCDON
LCDON
Out
LCD drive power on signal
85
LOGICON
NC
Out
LCD logic power on signal
86
GND
GND
In
GND
87
VDD
VCC
In
+5V
88
MA9
NC
Out
NC
89
MA8
MA8
Out
Memory address bus
90
MA7
MA7
Out
Memory address bus
91
MA6
MA6
Out
Memory address bus
92
MA5
MA5
Out
Memory address bus
93
MA4
MA4
Out
Memory address bus
92
MA3
MA3
Out
Memory address bus
91
MA2
MA2
Out
Memory address bus
92
MA5
MA5
Out
Memory address bus
93
MA4
MA4
Out
Memory address bus
94
MA3
MA3
Out
Memory address bus
95
MA2
MA2
Out
Memory address bus
96
MA1
MA1
Out
Memory address bus
97
MA0
MA0
Out
Memory address bus
98
GND
GND
In
GND
99
VDD
VCC
In
VCC
100
/RAS
/RASV
Out
RAS address strobe
101
/UCAS
/UCASV
Out
Upper CAS address strobe
102
/LCAS
/LCASV
Out
Lower CAS address strobe
103
/WE
/WEV
Out
Write enable
104
MD15
MD15
I/O
Memory data
105
MD14
MD14
I/O
Memory data
106
MD13
MD13
I/O
Memory data
107
MD12
MD12
I/O
Memory data
108
MD11
MD11
I/O
Memory data
109
MD10
MD10
I/O
Memory data
110
GND
GND
In
GND
111
VDD
VCC
In
+5V
112
MD9
MD9
I/O
Memory data
113
MD8
MD8
I/O
Memory data
114
MD7
MD7
I/O
Memory data
7 – 19