2) Block diagram
P47
P46
P45
P44
P43
P42
P41/TMCI
P40
P37
P36
P35
P34
P33
BREQ
BACK
WAIT
P27/A23
P26/A22
P25/A21
P24/A20
P23/A19
P22/A18
P21/A17
P20/A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AVCC
AVSS
MD2
MD1
MD0
RES
STBY
NMI
AS
RD
HWR
LWR
RFSH
EXTAL
XTAL
E
P17
P16
P15
P14
P13
P12
P11
P10
D15
D14
D13
D12
D11
D10
D9
D8
P57
P56
P55
P54
P53
P52
P51
P50
P67
P66
P65
P64
P63
P62
P61
P60
P73
P72
P71
P70
TXD2
RXD2
TXD1
RXD1
SCK2/IRQ3
SCK1/IRQ2
IRQ1
IRQ0
H8/500 CPU
DTC
Serial
communication
interface x 2ch
8bit timer
16bit free running
timer x 2ch
Refresh controller
Wait state
controller
A/D convertor
Interruption controller
Clock
oscillator
Watch
dog timer
Data bus
Port 1
Data bus (Lower)
Data bus (Upper)
Address bus
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Address bus
X
7 – 3