V5C Technical Manual
6-8
Board Status Register Two, and NVRAM Address Control.
Bit 0:
(R) P5 VME Backplane Detect (1 = P5 Present).
Bit 1:
(R) NVSRAM Store Flag (1 = Store in Progress).
Bit 2:
Reserved
Bit 3:
Reserved
Bit 4:
Reserved
Bit 5:
Reserved
Bit 6:
{W/R} NVSRAM Enable.
Bit 7:
{R} TB51 Detect. 1 = TB51 Present.
* These register bits are reserved for paging control of the NVSRAM. This
function is not implemented in this version of the equations
Board Status Register 2
Intel® Dual HiQVideo
TM
Accelerator Engine
7 6 5 4 3 2 1 0
TB51 NVSEN
RSV
RSV
RSV
RSV
STFL
BPP5
Figure 6-9
Board Status Register 2 (I/O 2A8H)
The 69030 graphics accelerator is designed to support high performance graphics
and video acceleration for all supported video resolutions, display types and
color modes. Primarily, you should not need to program the video controller
directly, because the Video BIOS provides functions for video operation through
interrupt 10H. These are fully defined in Section 3 of Advanced MS-DOS.
However, if it becomes necessary to program the controller directly, refer to the
Intel Corporation 69030 Databook.
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