V5C Technical Manual
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Full Universe IIB VMEbus Master/Slave Operation
The V5C was designed to provide both VMEbus Master and VMEbus Slave
capability. As such, it can initiate data transfers over the VMEbus and receive
data from other VMEbus Masters. A number of facilities have been provided to
enhance VMEbus Master and Slave operation.
The VMEbus interface provides 8 master and 8 slave VMEbus access paths. A
path configured as a slave allows access to the V5C System DRAM and other
local resources from the VMEbus. The interface can be configured to allow all,
part, or none of the local address space to be accessible, allowing local data to
be configured as inaccessible from the VMEbus.
An access path configured as a master allows the V5C to perform data transfers
on the VMEbus. A path can be configured to appear anywhere in available local
address space, and map anywhere on the VMEbus, providing for a very flexible
interface.
Byte Swapping Capability
The V5C features hardware implemented byte swapping. This allows for faster data
transfers than possible using software implemented byte swapping. Supported
modes of byte swapping are M32(no swapping), I32(Intel swapping), and I16(D16
byte swap). These modes can be specified for both master and slave transfers.
VMEbus System Controller Capability
The V5C can be software configured as a VMEbus System Controller, independent
of VMEbus Master or Slave operation. This is especially important if the V5C is
going to be the only CPU card in the VMEbus system. Also, the V5C can
automatically detect if it is in the VME slot one and turn on the System Controller
function.
Interrupter and Interrupt Handler
The Universe IIB chip provides a flexible scheme to map interrupts to either the
PCI bus or the VMEbus. The Universe IIB Interrupter provides an 8-bit STA-
TUS/ID to a VMEbus interrupt handler during the IACK cycle, and optionally
generates an internal interrupt to signal that the interrupt vector has been provid-
ed. A VMEbus interrupt can trigger the Universe IIB to generate a normal
VMEbus IACK cycle. When the IACK cycle is complete, the Universe IIB
releases the VMEbus and the interrupt vector is received by the PCI resource
servicing the interrupt output.
Universe
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